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Ravi Gunasekarandavem330
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net: ethernet: ti: davinci_mdio: Add workaround for errata i2329
On the CPSW and ICSS peripherals, there is a possibility that the MDIO interface returns corrupt data on MDIO reads or writes incorrect data on MDIO writes. There is also a possibility for the MDIO interface to become unavailable until the next peripheral reset. The workaround is to configure the MDIO in manual mode and disable the MDIO state machine and emulate the MDIO protocol by reading and writing appropriate fields in MDIO_MANUAL_IF_REG register of the MDIO controller to manipulate the MDIO clock and data pins. More details about the errata i2329 and the workaround is available in: https://www.ti.com/lit/er/sprz487a/sprz487a.pdf Add implementation to disable MDIO state machine, configure MDIO in manual mode and achieve MDIO read and writes via MDIO Bitbanging Signed-off-by: Ravi Gunasekaran <[email protected]> Reported-by: kernel test robot <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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drivers/net/ethernet/ti/davinci_mdio.c

Lines changed: 231 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,8 @@
2626
#include <linux/of_device.h>
2727
#include <linux/of_mdio.h>
2828
#include <linux/pinctrl/consumer.h>
29+
#include <linux/mdio-bitbang.h>
30+
#include <linux/sys_soc.h>
2931

3032
/*
3133
* This timeout definition is a worst-case ultra defensive measure against
@@ -41,6 +43,7 @@
4143

4244
struct davinci_mdio_of_param {
4345
int autosuspend_delay_ms;
46+
bool manual_mode;
4447
};
4548

4649
struct davinci_mdio_regs {
@@ -49,6 +52,15 @@ struct davinci_mdio_regs {
4952
#define CONTROL_IDLE BIT(31)
5053
#define CONTROL_ENABLE BIT(30)
5154
#define CONTROL_MAX_DIV (0xffff)
55+
#define CONTROL_CLKDIV GENMASK(15, 0)
56+
57+
#define MDIO_MAN_MDCLK_O BIT(2)
58+
#define MDIO_MAN_OE BIT(1)
59+
#define MDIO_MAN_PIN BIT(0)
60+
#define MDIO_MANUALMODE BIT(31)
61+
62+
#define MDIO_PIN 0
63+
5264

5365
u32 alive;
5466
u32 link;
@@ -59,7 +71,9 @@ struct davinci_mdio_regs {
5971
u32 userintmasked;
6072
u32 userintmaskset;
6173
u32 userintmaskclr;
62-
u32 __reserved_1[20];
74+
u32 manualif;
75+
u32 poll;
76+
u32 __reserved_1[18];
6377

6478
struct {
6579
u32 access;
@@ -79,6 +93,7 @@ static const struct mdio_platform_data default_pdata = {
7993

8094
struct davinci_mdio_data {
8195
struct mdio_platform_data pdata;
96+
struct mdiobb_ctrl bb_ctrl;
8297
struct davinci_mdio_regs __iomem *regs;
8398
struct clk *clk;
8499
struct device *dev;
@@ -90,6 +105,7 @@ struct davinci_mdio_data {
90105
*/
91106
bool skip_scan;
92107
u32 clk_div;
108+
bool manual_mode;
93109
};
94110

95111
static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
@@ -128,16 +144,134 @@ static void davinci_mdio_enable(struct davinci_mdio_data *data)
128144
writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
129145
}
130146

131-
static int davinci_mdio_reset(struct mii_bus *bus)
147+
static void davinci_mdio_disable(struct davinci_mdio_data *data)
148+
{
149+
u32 reg;
150+
151+
/* Disable MDIO state machine */
152+
reg = readl(&data->regs->control);
153+
154+
reg &= ~CONTROL_CLKDIV;
155+
reg |= data->clk_div;
156+
157+
reg &= ~CONTROL_ENABLE;
158+
writel(reg, &data->regs->control);
159+
}
160+
161+
static void davinci_mdio_enable_manual_mode(struct davinci_mdio_data *data)
162+
{
163+
u32 reg;
164+
/* set manual mode */
165+
reg = readl(&data->regs->poll);
166+
reg |= MDIO_MANUALMODE;
167+
writel(reg, &data->regs->poll);
168+
}
169+
170+
static void davinci_set_mdc(struct mdiobb_ctrl *ctrl, int level)
171+
{
172+
struct davinci_mdio_data *data;
173+
u32 reg;
174+
175+
data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
176+
reg = readl(&data->regs->manualif);
177+
178+
if (level)
179+
reg |= MDIO_MAN_MDCLK_O;
180+
else
181+
reg &= ~MDIO_MAN_MDCLK_O;
182+
183+
writel(reg, &data->regs->manualif);
184+
}
185+
186+
static void davinci_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
187+
{
188+
struct davinci_mdio_data *data;
189+
u32 reg;
190+
191+
data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
192+
reg = readl(&data->regs->manualif);
193+
194+
if (output)
195+
reg |= MDIO_MAN_OE;
196+
else
197+
reg &= ~MDIO_MAN_OE;
198+
199+
writel(reg, &data->regs->manualif);
200+
}
201+
202+
static void davinci_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
203+
{
204+
struct davinci_mdio_data *data;
205+
u32 reg;
206+
207+
data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
208+
reg = readl(&data->regs->manualif);
209+
210+
if (value)
211+
reg |= MDIO_MAN_PIN;
212+
else
213+
reg &= ~MDIO_MAN_PIN;
214+
215+
writel(reg, &data->regs->manualif);
216+
}
217+
218+
static int davinci_get_mdio_data(struct mdiobb_ctrl *ctrl)
219+
{
220+
struct davinci_mdio_data *data;
221+
unsigned long reg;
222+
223+
data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
224+
reg = readl(&data->regs->manualif);
225+
return test_bit(MDIO_PIN, &reg);
226+
}
227+
228+
static int davinci_mdiobb_read(struct mii_bus *bus, int phy, int reg)
229+
{
230+
int ret;
231+
232+
ret = pm_runtime_resume_and_get(bus->parent);
233+
if (ret < 0)
234+
return ret;
235+
236+
ret = mdiobb_read(bus, phy, reg);
237+
238+
pm_runtime_mark_last_busy(bus->parent);
239+
pm_runtime_put_autosuspend(bus->parent);
240+
241+
return ret;
242+
}
243+
244+
static int davinci_mdiobb_write(struct mii_bus *bus, int phy, int reg,
245+
u16 val)
246+
{
247+
int ret;
248+
249+
ret = pm_runtime_resume_and_get(bus->parent);
250+
if (ret < 0)
251+
return ret;
252+
253+
ret = mdiobb_write(bus, phy, reg, val);
254+
255+
pm_runtime_mark_last_busy(bus->parent);
256+
pm_runtime_put_autosuspend(bus->parent);
257+
258+
return ret;
259+
}
260+
261+
static int davinci_mdio_common_reset(struct davinci_mdio_data *data)
132262
{
133-
struct davinci_mdio_data *data = bus->priv;
134263
u32 phy_mask, ver;
135264
int ret;
136265

137266
ret = pm_runtime_resume_and_get(data->dev);
138267
if (ret < 0)
139268
return ret;
140269

270+
if (data->manual_mode) {
271+
davinci_mdio_disable(data);
272+
davinci_mdio_enable_manual_mode(data);
273+
}
274+
141275
/* wait for scan logic to settle */
142276
msleep(PHY_MAX_ADDR * data->access_time);
143277

@@ -171,6 +305,23 @@ static int davinci_mdio_reset(struct mii_bus *bus)
171305
return 0;
172306
}
173307

308+
static int davinci_mdio_reset(struct mii_bus *bus)
309+
{
310+
struct davinci_mdio_data *data = bus->priv;
311+
312+
return davinci_mdio_common_reset(data);
313+
}
314+
315+
static int davinci_mdiobb_reset(struct mii_bus *bus)
316+
{
317+
struct mdiobb_ctrl *ctrl = bus->priv;
318+
struct davinci_mdio_data *data;
319+
320+
data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
321+
322+
return davinci_mdio_common_reset(data);
323+
}
324+
174325
/* wait until hardware is ready for another user access */
175326
static inline int wait_for_user_access(struct davinci_mdio_data *data)
176327
{
@@ -318,6 +469,28 @@ static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
318469
return 0;
319470
}
320471

472+
struct k3_mdio_soc_data {
473+
bool manual_mode;
474+
};
475+
476+
static const struct k3_mdio_soc_data am65_mdio_soc_data = {
477+
.manual_mode = true,
478+
};
479+
480+
static const struct soc_device_attribute k3_mdio_socinfo[] = {
481+
{ .family = "AM62X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
482+
{ .family = "AM64X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
483+
{ .family = "AM64X", .revision = "SR2.0", .data = &am65_mdio_soc_data },
484+
{ .family = "AM65X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
485+
{ .family = "AM65X", .revision = "SR2.0", .data = &am65_mdio_soc_data },
486+
{ .family = "J7200", .revision = "SR1.0", .data = &am65_mdio_soc_data },
487+
{ .family = "J7200", .revision = "SR2.0", .data = &am65_mdio_soc_data },
488+
{ .family = "J721E", .revision = "SR1.0", .data = &am65_mdio_soc_data },
489+
{ .family = "J721E", .revision = "SR2.0", .data = &am65_mdio_soc_data },
490+
{ .family = "J721S2", .revision = "SR1.0", .data = &am65_mdio_soc_data},
491+
{ /* sentinel */ },
492+
};
493+
321494
#if IS_ENABLED(CONFIG_OF)
322495
static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
323496
.autosuspend_delay_ms = 100,
@@ -331,6 +504,14 @@ static const struct of_device_id davinci_mdio_of_mtable[] = {
331504
MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
332505
#endif
333506

507+
static const struct mdiobb_ops davinci_mdiobb_ops = {
508+
.owner = THIS_MODULE,
509+
.set_mdc = davinci_set_mdc,
510+
.set_mdio_dir = davinci_set_mdio_dir,
511+
.set_mdio_data = davinci_set_mdio_data,
512+
.get_mdio_data = davinci_get_mdio_data,
513+
};
514+
334515
static int davinci_mdio_probe(struct platform_device *pdev)
335516
{
336517
struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
@@ -345,7 +526,26 @@ static int davinci_mdio_probe(struct platform_device *pdev)
345526
if (!data)
346527
return -ENOMEM;
347528

348-
data->bus = devm_mdiobus_alloc(dev);
529+
data->manual_mode = false;
530+
data->bb_ctrl.ops = &davinci_mdiobb_ops;
531+
532+
if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
533+
const struct soc_device_attribute *soc_match_data;
534+
535+
soc_match_data = soc_device_match(k3_mdio_socinfo);
536+
if (soc_match_data && soc_match_data->data) {
537+
const struct k3_mdio_soc_data *socdata =
538+
soc_match_data->data;
539+
540+
data->manual_mode = socdata->manual_mode;
541+
}
542+
}
543+
544+
if (data->manual_mode)
545+
data->bus = alloc_mdio_bitbang(&data->bb_ctrl);
546+
else
547+
data->bus = devm_mdiobus_alloc(dev);
548+
349549
if (!data->bus) {
350550
dev_err(dev, "failed to alloc mii bus\n");
351551
return -ENOMEM;
@@ -371,11 +571,20 @@ static int davinci_mdio_probe(struct platform_device *pdev)
371571
}
372572

373573
data->bus->name = dev_name(dev);
374-
data->bus->read = davinci_mdio_read;
375-
data->bus->write = davinci_mdio_write;
376-
data->bus->reset = davinci_mdio_reset;
574+
575+
if (data->manual_mode) {
576+
data->bus->read = davinci_mdiobb_read;
577+
data->bus->write = davinci_mdiobb_write;
578+
data->bus->reset = davinci_mdiobb_reset;
579+
580+
dev_info(dev, "Configuring MDIO in manual mode\n");
581+
} else {
582+
data->bus->read = davinci_mdio_read;
583+
data->bus->write = davinci_mdio_write;
584+
data->bus->reset = davinci_mdio_reset;
585+
data->bus->priv = data;
586+
}
377587
data->bus->parent = dev;
378-
data->bus->priv = data;
379588

380589
data->clk = devm_clk_get(dev, "fck");
381590
if (IS_ERR(data->clk)) {
@@ -433,9 +642,13 @@ static int davinci_mdio_remove(struct platform_device *pdev)
433642
{
434643
struct davinci_mdio_data *data = platform_get_drvdata(pdev);
435644

436-
if (data->bus)
645+
if (data->bus) {
437646
mdiobus_unregister(data->bus);
438647

648+
if (data->manual_mode)
649+
free_mdio_bitbang(data->bus);
650+
}
651+
439652
pm_runtime_dont_use_autosuspend(&pdev->dev);
440653
pm_runtime_disable(&pdev->dev);
441654

@@ -452,7 +665,9 @@ static int davinci_mdio_runtime_suspend(struct device *dev)
452665
ctrl = readl(&data->regs->control);
453666
ctrl &= ~CONTROL_ENABLE;
454667
writel(ctrl, &data->regs->control);
455-
wait_for_idle(data);
668+
669+
if (!data->manual_mode)
670+
wait_for_idle(data);
456671

457672
return 0;
458673
}
@@ -461,7 +676,12 @@ static int davinci_mdio_runtime_resume(struct device *dev)
461676
{
462677
struct davinci_mdio_data *data = dev_get_drvdata(dev);
463678

464-
davinci_mdio_enable(data);
679+
if (data->manual_mode) {
680+
davinci_mdio_disable(data);
681+
davinci_mdio_enable_manual_mode(data);
682+
} else {
683+
davinci_mdio_enable(data);
684+
}
465685
return 0;
466686
}
467687
#endif

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