@@ -85,36 +85,37 @@ static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
85
85
u32 mapped ;
86
86
u32 size ;
87
87
} fixed_map [] = {
88
- { 0x00400000 , 0x80000 , 0x10000 }, /* WF_MCU_SYSRAM */
89
- { 0x00410000 , 0x90000 , 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
90
- { 0x40000000 , 0x70000 , 0x10000 }, /* WF_UMAC_SYSRAM */
88
+ { 0x820d0000 , 0x30000 , 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
89
+ { 0x820ed000 , 0x24800 , 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
90
+ { 0x820e4000 , 0x21000 , 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
91
+ { 0x820e7000 , 0x21e00 , 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
92
+ { 0x820eb000 , 0x24200 , 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
93
+ { 0x820e2000 , 0x20800 , 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
94
+ { 0x820e3000 , 0x20c00 , 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
95
+ { 0x820e5000 , 0x21400 , 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
96
+ { 0x00400000 , 0x80000 , 0x10000 }, /* WF_MCU_SYSRAM */
97
+ { 0x00410000 , 0x90000 , 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
98
+ { 0x40000000 , 0x70000 , 0x10000 }, /* WF_UMAC_SYSRAM */
91
99
{ 0x54000000 , 0x02000 , 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
92
100
{ 0x55000000 , 0x03000 , 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
93
101
{ 0x58000000 , 0x06000 , 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
94
102
{ 0x59000000 , 0x07000 , 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
95
103
{ 0x7c000000 , 0xf0000 , 0x10000 }, /* CONN_INFRA */
96
104
{ 0x7c020000 , 0xd0000 , 0x10000 }, /* CONN_INFRA, WFDMA */
97
- { 0x7c060000 , 0xe0000 , 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
105
+ { 0x7c060000 , 0xe0000 , 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
98
106
{ 0x80020000 , 0xb0000 , 0x10000 }, /* WF_TOP_MISC_OFF */
99
107
{ 0x81020000 , 0xc0000 , 0x10000 }, /* WF_TOP_MISC_ON */
100
108
{ 0x820c0000 , 0x08000 , 0x4000 }, /* WF_UMAC_TOP (PLE) */
101
109
{ 0x820c8000 , 0x0c000 , 0x2000 }, /* WF_UMAC_TOP (PSE) */
102
- { 0x820cc000 , 0x0e000 , 0x2000 }, /* WF_UMAC_TOP (PP) */
110
+ { 0x820cc000 , 0x0e000 , 0x1000 }, /* WF_UMAC_TOP (PP) */
111
+ { 0x820cd000 , 0x0f000 , 0x1000 }, /* WF_MDP_TOP */
103
112
{ 0x820ce000 , 0x21c00 , 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
104
113
{ 0x820cf000 , 0x22000 , 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
105
- { 0x820d0000 , 0x30000 , 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
106
114
{ 0x820e0000 , 0x20000 , 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
107
115
{ 0x820e1000 , 0x20400 , 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
108
- { 0x820e2000 , 0x20800 , 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
109
- { 0x820e3000 , 0x20c00 , 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
110
- { 0x820e4000 , 0x21000 , 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
111
- { 0x820e5000 , 0x21400 , 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
112
- { 0x820e7000 , 0x21e00 , 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
113
116
{ 0x820e9000 , 0x23400 , 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
114
117
{ 0x820ea000 , 0x24000 , 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
115
- { 0x820eb000 , 0x24200 , 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
116
118
{ 0x820ec000 , 0x24600 , 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
117
- { 0x820ed000 , 0x24800 , 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
118
119
{ 0x820f0000 , 0xa0000 , 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
119
120
{ 0x820f1000 , 0xa0600 , 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
120
121
{ 0x820f2000 , 0xa0800 , 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
0 commit comments