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1 parent 3dfedf0 commit e8a7cd6Copy full SHA for e8a7cd6
lib/SILGen/SILGen.cpp
@@ -1210,7 +1210,7 @@ void SILGenModule::visitVarDecl(VarDecl *vd) {
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auto accessor = vd->getAccessor(kind);
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if (!accessor) return;
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- // Only eit the accessor if it wasn't added to the surrounding decl
+ // Only emit the accessor if it wasn't added to the surrounding decl
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// list by the parser. We can test that easily by looking at the impl
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// info, since all of these accessors have a corresponding access kind
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// whose impl should definitely point at the accessor if it was parsed.
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