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[RISCV] Add integer RISCVISD::SELECT_CC to canCreateUndefOrPoison and isGuaranteedNotToBeUndefOrPoison. (llvm#84693)
Integer RISCVISD::SELECT_CC doesn't create poison. If none of the, operands are poison, the result is not poison. This allows ISD::FREEZE to be hoisted above RISCVISD::SELECT_CC.
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8 files changed

+702
-756
lines changed

8 files changed

+702
-756
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17093,6 +17093,23 @@ unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
1709317093
return 1;
1709417094
}
1709517095

17096+
bool RISCVTargetLowering::canCreateUndefOrPoisonForTargetNode(
17097+
SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
17098+
bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {
17099+
17100+
// TODO: Add more target nodes.
17101+
switch (Op.getOpcode()) {
17102+
case RISCVISD::SELECT_CC:
17103+
// Integer select_cc cannot create poison.
17104+
// TODO: What are the FP poison semantics?
17105+
// TODO: This instruction blocks poison from the unselected operand, can
17106+
// we do anything with that?
17107+
return !Op.getValueType().isInteger();
17108+
}
17109+
return TargetLowering::canCreateUndefOrPoisonForTargetNode(
17110+
Op, DemandedElts, DAG, PoisonOnly, ConsiderFlags, Depth);
17111+
}
17112+
1709617113
const Constant *
1709717114
RISCVTargetLowering::getTargetConstantFromLoad(LoadSDNode *Ld) const {
1709817115
assert(Ld && "Unexpected null LoadSDNode");

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -585,6 +585,12 @@ class RISCVTargetLowering : public TargetLowering {
585585
const SelectionDAG &DAG,
586586
unsigned Depth) const override;
587587

588+
bool canCreateUndefOrPoisonForTargetNode(SDValue Op,
589+
const APInt &DemandedElts,
590+
const SelectionDAG &DAG,
591+
bool PoisonOnly, bool ConsiderFlags,
592+
unsigned Depth) const override;
593+
588594
const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
589595

590596
// This method returns the name of a target specific DAG node.

‎llvm/test/CodeGen/RISCV/double-convert.ll

Lines changed: 54 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -683,47 +683,41 @@ define i64 @fcvt_l_d(double %a) nounwind {
683683
define i64 @fcvt_l_d_sat(double %a) nounwind {
684684
; RV32IFD-LABEL: fcvt_l_d_sat:
685685
; RV32IFD: # %bb.0: # %start
686-
; RV32IFD-NEXT: addi sp, sp, -32
687-
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
688-
; RV32IFD-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
689-
; RV32IFD-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
690-
; RV32IFD-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
691-
; RV32IFD-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
686+
; RV32IFD-NEXT: addi sp, sp, -16
687+
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
688+
; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
692689
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
693690
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_0)
694691
; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
695-
; RV32IFD-NEXT: lui a0, %hi(.LCPI12_1)
696-
; RV32IFD-NEXT: fld fa4, %lo(.LCPI12_1)(a0)
697692
; RV32IFD-NEXT: fmv.d fs0, fa0
698-
; RV32IFD-NEXT: flt.d s0, fa5, fa0
699-
; RV32IFD-NEXT: neg s1, s0
700-
; RV32IFD-NEXT: fle.d s2, fa4, fa0
701-
; RV32IFD-NEXT: neg s3, s2
693+
; RV32IFD-NEXT: fle.d s0, fa5, fa0
702694
; RV32IFD-NEXT: call __fixdfdi
703-
; RV32IFD-NEXT: and a0, s3, a0
704-
; RV32IFD-NEXT: or a0, s1, a0
705-
; RV32IFD-NEXT: feq.d a2, fs0, fs0
706-
; RV32IFD-NEXT: neg a2, a2
707-
; RV32IFD-NEXT: lui a4, 524288
708-
; RV32IFD-NEXT: li a5, 1
709695
; RV32IFD-NEXT: lui a3, 524288
710-
; RV32IFD-NEXT: bne s2, a5, .LBB12_2
696+
; RV32IFD-NEXT: li a4, 1
697+
; RV32IFD-NEXT: lui a2, 524288
698+
; RV32IFD-NEXT: bne s0, a4, .LBB12_2
711699
; RV32IFD-NEXT: # %bb.1: # %start
712-
; RV32IFD-NEXT: mv a3, a1
700+
; RV32IFD-NEXT: mv a2, a1
713701
; RV32IFD-NEXT: .LBB12_2: # %start
714-
; RV32IFD-NEXT: and a0, a2, a0
715-
; RV32IFD-NEXT: beqz s0, .LBB12_4
702+
; RV32IFD-NEXT: lui a1, %hi(.LCPI12_1)
703+
; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a1)
704+
; RV32IFD-NEXT: flt.d a4, fa5, fs0
705+
; RV32IFD-NEXT: beqz a4, .LBB12_4
716706
; RV32IFD-NEXT: # %bb.3:
717-
; RV32IFD-NEXT: addi a3, a4, -1
707+
; RV32IFD-NEXT: addi a2, a3, -1
718708
; RV32IFD-NEXT: .LBB12_4: # %start
719-
; RV32IFD-NEXT: and a1, a2, a3
720-
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
721-
; RV32IFD-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
722-
; RV32IFD-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
723-
; RV32IFD-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
724-
; RV32IFD-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
709+
; RV32IFD-NEXT: feq.d a1, fs0, fs0
710+
; RV32IFD-NEXT: neg a3, a1
711+
; RV32IFD-NEXT: and a1, a3, a2
712+
; RV32IFD-NEXT: neg a2, a4
713+
; RV32IFD-NEXT: neg a4, s0
714+
; RV32IFD-NEXT: and a0, a4, a0
715+
; RV32IFD-NEXT: or a0, a2, a0
716+
; RV32IFD-NEXT: and a0, a3, a0
717+
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
718+
; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
725719
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
726-
; RV32IFD-NEXT: addi sp, sp, 32
720+
; RV32IFD-NEXT: addi sp, sp, 16
727721
; RV32IFD-NEXT: ret
728722
;
729723
; RV64IFD-LABEL: fcvt_l_d_sat:
@@ -737,48 +731,44 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
737731
;
738732
; RV32IZFINXZDINX-LABEL: fcvt_l_d_sat:
739733
; RV32IZFINXZDINX: # %bb.0: # %start
740-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
741-
; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
742-
; RV32IZFINXZDINX-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
743-
; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
744-
; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
745-
; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
746-
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
747-
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2)
748-
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
734+
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
735+
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
736+
; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
737+
; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
749738
; RV32IZFINXZDINX-NEXT: mv s1, a1
750739
; RV32IZFINXZDINX-NEXT: mv s0, a0
751-
; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0
752-
; RV32IZFINXZDINX-NEXT: neg s3, s2
753740
; RV32IZFINXZDINX-NEXT: call __fixdfdi
754-
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_1)
755-
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_1+4)(a2)
756-
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_1)(a2)
757-
; RV32IZFINXZDINX-NEXT: and a0, s3, a0
758-
; RV32IZFINXZDINX-NEXT: flt.d a3, a2, s0
759-
; RV32IZFINXZDINX-NEXT: neg a2, a3
760-
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
761-
; RV32IZFINXZDINX-NEXT: feq.d a2, s0, s0
762-
; RV32IZFINXZDINX-NEXT: neg a2, a2
741+
; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0)
742+
; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI12_0+4)(a2)
743+
; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a2)
744+
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
763745
; RV32IZFINXZDINX-NEXT: lui a5, 524288
764-
; RV32IZFINXZDINX-NEXT: li a6, 1
765-
; RV32IZFINXZDINX-NEXT: lui a4, 524288
766-
; RV32IZFINXZDINX-NEXT: bne s2, a6, .LBB12_2
746+
; RV32IZFINXZDINX-NEXT: li a4, 1
747+
; RV32IZFINXZDINX-NEXT: lui a3, 524288
748+
; RV32IZFINXZDINX-NEXT: bne a2, a4, .LBB12_2
767749
; RV32IZFINXZDINX-NEXT: # %bb.1: # %start
768-
; RV32IZFINXZDINX-NEXT: mv a4, a1
750+
; RV32IZFINXZDINX-NEXT: mv a3, a1
769751
; RV32IZFINXZDINX-NEXT: .LBB12_2: # %start
770-
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
771-
; RV32IZFINXZDINX-NEXT: beqz a3, .LBB12_4
752+
; RV32IZFINXZDINX-NEXT: lui a1, %hi(.LCPI12_1)
753+
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI12_1)(a1)
754+
; RV32IZFINXZDINX-NEXT: lw a7, %lo(.LCPI12_1+4)(a1)
755+
; RV32IZFINXZDINX-NEXT: flt.d a4, a6, s0
756+
; RV32IZFINXZDINX-NEXT: beqz a4, .LBB12_4
772757
; RV32IZFINXZDINX-NEXT: # %bb.3:
773-
; RV32IZFINXZDINX-NEXT: addi a4, a5, -1
758+
; RV32IZFINXZDINX-NEXT: addi a3, a5, -1
774759
; RV32IZFINXZDINX-NEXT: .LBB12_4: # %start
775-
; RV32IZFINXZDINX-NEXT: and a1, a2, a4
776-
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
777-
; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
778-
; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
779-
; RV32IZFINXZDINX-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
780-
; RV32IZFINXZDINX-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
781-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
760+
; RV32IZFINXZDINX-NEXT: feq.d a1, s0, s0
761+
; RV32IZFINXZDINX-NEXT: neg a5, a1
762+
; RV32IZFINXZDINX-NEXT: and a1, a5, a3
763+
; RV32IZFINXZDINX-NEXT: neg a2, a2
764+
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
765+
; RV32IZFINXZDINX-NEXT: neg a2, a4
766+
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
767+
; RV32IZFINXZDINX-NEXT: and a0, a5, a0
768+
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
769+
; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
770+
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
771+
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
782772
; RV32IZFINXZDINX-NEXT: ret
783773
;
784774
; RV64IZFINXZDINX-LABEL: fcvt_l_d_sat:

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