Skip to content
This repository was archived by the owner on Apr 23, 2020. It is now read-only.

Commit 8fe02fa

Browse files
rotaterightrotateright
committed
[SelectionDAG] fix bug in translating funnel shift with non-power-of-2 type
The bug is visible in the constant-folded x86 tests. We can't use the negated shift amount when the type is not power-of-2: https://rise4fun.com/Alive/US1r ...so in that case, use the regular lowering that includes a select to guard against a shift-by-bitwidth. This path is improved by only calculating the modulo shift amount once now. Also, improve the rotate (with power-of-2 size) lowering to use a negate rather than subtract from bitwidth. This improves the codegen whether we have a rotate instruction or not (although we can still see that we're not matching to a legal rotate in all cases). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338592 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent 887eb8d commit 8fe02fa

File tree

7 files changed

+217
-312
lines changed

7 files changed

+217
-312
lines changed

‎lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 39 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -5693,43 +5693,51 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
56935693
SDValue Y = getValue(I.getArgOperand(1));
56945694
SDValue Z = getValue(I.getArgOperand(2));
56955695
EVT VT = X.getValueType();
5696+
SDValue BitWidthC = DAG.getConstant(VT.getScalarSizeInBits(), sdl, VT);
5697+
SDValue Zero = DAG.getConstant(0, sdl, VT);
5698+
SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC);
56965699

5697-
// When X == Y, this is rotate. Create the node directly if legal.
5698-
// TODO: This should also be done if the operation is custom, but we have
5699-
// to make sure targets are handling the modulo shift amount as expected.
5700-
// TODO: If the rotate direction (left or right) corresponding to the shift
5701-
// is not available, adjust the shift value and invert the direction.
5702-
auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
5703-
if (X == Y && TLI.isOperationLegal(RotateOpcode, VT)) {
5704-
setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z));
5700+
// When X == Y, this is rotate. If the data type has a power-of-2 size, we
5701+
// avoid the select that is necessary in the general case to filter out
5702+
// the 0-shift possibility that leads to UB.
5703+
if (X == Y && isPowerOf2_32(VT.getScalarSizeInBits())) {
5704+
// TODO: This should also be done if the operation is custom, but we have
5705+
// to make sure targets are handling the modulo shift amount as expected.
5706+
// TODO: If the rotate direction (left or right) corresponding to the
5707+
// shift is not available, adjust the shift value and invert the
5708+
// direction.
5709+
auto RotateOpcode = IsFSHL ? ISD::ROTL : ISD::ROTR;
5710+
if (TLI.isOperationLegal(RotateOpcode, VT)) {
5711+
setValue(&I, DAG.getNode(RotateOpcode, sdl, VT, X, Z));
5712+
return nullptr;
5713+
}
5714+
// fshl (rotl): (X << (Z % BW)) | (X >> ((0 - Z) % BW))
5715+
// fshr (rotr): (X << ((0 - Z) % BW)) | (X >> (Z % BW))
5716+
SDValue NegZ = DAG.getNode(ISD::SUB, sdl, VT, Zero, Z);
5717+
SDValue NShAmt = DAG.getNode(ISD::UREM, sdl, VT, NegZ, BitWidthC);
5718+
SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : NShAmt);
5719+
SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, X, IsFSHL ? NShAmt : ShAmt);
5720+
setValue(&I, DAG.getNode(ISD::OR, sdl, VT, ShX, ShY));
57055721
return nullptr;
57065722
}
57075723

5708-
// Get the shift amount and inverse shift amount, modulo the bit-width.
5709-
SDValue BitWidthC = DAG.getConstant(VT.getScalarSizeInBits(), sdl, VT);
5710-
SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC);
5711-
SDValue NegZ = DAG.getNode(ISD::SUB, sdl, VT, BitWidthC, Z);
5712-
SDValue InvShAmt = DAG.getNode(ISD::UREM, sdl, VT, NegZ, BitWidthC);
5713-
5714-
// fshl: (X << (Z % BW)) | (Y >> ((BW - Z) % BW))
5715-
// fshr: (X << ((BW - Z) % BW)) | (Y >> (Z % BW))
5724+
// fshl: (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
5725+
// fshr: (X << (BW - (Z % BW))) | (Y >> (Z % BW))
5726+
SDValue InvShAmt = DAG.getNode(ISD::SUB, sdl, VT, BitWidthC, ShAmt);
57165727
SDValue ShX = DAG.getNode(ISD::SHL, sdl, VT, X, IsFSHL ? ShAmt : InvShAmt);
57175728
SDValue ShY = DAG.getNode(ISD::SRL, sdl, VT, Y, IsFSHL ? InvShAmt : ShAmt);
5718-
SDValue Res = DAG.getNode(ISD::OR, sdl, VT, ShX, ShY);
5719-
5720-
// If (Z % BW == 0), then (BW - Z) % BW is also zero, so the result would
5721-
// be X | Y. If X == Y (rotate), that's fine. If not, we have to select.
5722-
if (X != Y) {
5723-
SDValue Zero = DAG.getConstant(0, sdl, VT);
5724-
EVT CCVT = MVT::i1;
5725-
if (VT.isVector())
5726-
CCVT = EVT::getVectorVT(*Context, CCVT, VT.getVectorNumElements());
5727-
// For fshl, 0 shift returns the 1st arg (X).
5728-
// For fshr, 0 shift returns the 2nd arg (Y).
5729-
SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ);
5730-
Res = DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Res);
5731-
}
5732-
setValue(&I, Res);
5729+
SDValue Or = DAG.getNode(ISD::OR, sdl, VT, ShX, ShY);
5730+
5731+
// If (Z % BW == 0), then the opposite direction shift is shift-by-bitwidth,
5732+
// and that is undefined. We must compare and select to avoid UB.
5733+
EVT CCVT = MVT::i1;
5734+
if (VT.isVector())
5735+
CCVT = EVT::getVectorVT(*Context, CCVT, VT.getVectorNumElements());
5736+
5737+
// For fshl, 0-shift returns the 1st arg (X).
5738+
// For fshr, 0-shift returns the 2nd arg (Y).
5739+
SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ);
5740+
setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or));
57335741
return nullptr;
57345742
}
57355743
case Intrinsic::stacksave: {

‎test/CodeGen/AArch64/funnel-shift-rot.ll

Lines changed: 17 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -40,8 +40,7 @@ define i64 @rotl_i64_const_shift(i64 %x) {
4040
define i16 @rotl_i16(i16 %x, i16 %z) {
4141
; CHECK-LABEL: rotl_i16:
4242
; CHECK: // %bb.0:
43-
; CHECK-NEXT: orr w10, wzr, #0x10
44-
; CHECK-NEXT: sub w10, w10, w1
43+
; CHECK-NEXT: neg w10, w1
4544
; CHECK-NEXT: and w8, w0, #0xffff
4645
; CHECK-NEXT: and w9, w1, #0xf
4746
; CHECK-NEXT: and w10, w10, #0xf
@@ -56,8 +55,7 @@ define i16 @rotl_i16(i16 %x, i16 %z) {
5655
define i32 @rotl_i32(i32 %x, i32 %z) {
5756
; CHECK-LABEL: rotl_i32:
5857
; CHECK: // %bb.0:
59-
; CHECK-NEXT: orr w8, wzr, #0x20
60-
; CHECK-NEXT: sub w8, w8, w1
58+
; CHECK-NEXT: neg w8, w1
6159
; CHECK-NEXT: ror w0, w0, w8
6260
; CHECK-NEXT: ret
6361
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
@@ -67,8 +65,7 @@ define i32 @rotl_i32(i32 %x, i32 %z) {
6765
define i64 @rotl_i64(i64 %x, i64 %z) {
6866
; CHECK-LABEL: rotl_i64:
6967
; CHECK: // %bb.0:
70-
; CHECK-NEXT: orr w9, wzr, #0x40
71-
; CHECK-NEXT: sub w9, w9, w1
68+
; CHECK-NEXT: neg w9, w1
7269
; CHECK-NEXT: lsl x8, x0, x1
7370
; CHECK-NEXT: lsr x9, x0, x9
7471
; CHECK-NEXT: orr x0, x8, x9
@@ -83,14 +80,13 @@ define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
8380
; CHECK-LABEL: rotl_v4i32:
8481
; CHECK: // %bb.0:
8582
; CHECK-NEXT: movi v2.4s, #31
86-
; CHECK-NEXT: movi v3.4s, #32
87-
; CHECK-NEXT: and v4.16b, v1.16b, v2.16b
88-
; CHECK-NEXT: sub v1.4s, v3.4s, v1.4s
83+
; CHECK-NEXT: neg v3.4s, v1.4s
8984
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
90-
; CHECK-NEXT: neg v1.4s, v1.4s
91-
; CHECK-NEXT: ushl v3.4s, v0.4s, v4.4s
92-
; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
93-
; CHECK-NEXT: orr v0.16b, v3.16b, v0.16b
85+
; CHECK-NEXT: and v2.16b, v3.16b, v2.16b
86+
; CHECK-NEXT: neg v2.4s, v2.4s
87+
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
88+
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
89+
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
9490
; CHECK-NEXT: ret
9591
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
9692
ret <4 x i32> %f
@@ -140,10 +136,9 @@ define i16 @rotr_i16(i16 %x, i16 %z) {
140136
; CHECK: // %bb.0:
141137
; CHECK-NEXT: and w8, w0, #0xffff
142138
; CHECK-NEXT: and w9, w1, #0xf
143-
; CHECK-NEXT: orr w10, wzr, #0x10
139+
; CHECK-NEXT: neg w10, w1
144140
; CHECK-NEXT: lsr w8, w8, w9
145-
; CHECK-NEXT: sub w9, w10, w1
146-
; CHECK-NEXT: and w9, w9, #0xf
141+
; CHECK-NEXT: and w9, w10, #0xf
147142
; CHECK-NEXT: lsl w9, w0, w9
148143
; CHECK-NEXT: orr w0, w9, w8
149144
; CHECK-NEXT: ret
@@ -175,14 +170,13 @@ define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
175170
; CHECK-LABEL: rotr_v4i32:
176171
; CHECK: // %bb.0:
177172
; CHECK-NEXT: movi v2.4s, #31
178-
; CHECK-NEXT: movi v3.4s, #32
179-
; CHECK-NEXT: and v4.16b, v1.16b, v2.16b
180-
; CHECK-NEXT: sub v1.4s, v3.4s, v1.4s
181-
; CHECK-NEXT: neg v3.4s, v4.4s
173+
; CHECK-NEXT: neg v3.4s, v1.4s
182174
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
183-
; CHECK-NEXT: ushl v2.4s, v0.4s, v3.4s
184-
; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
185-
; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
175+
; CHECK-NEXT: and v2.16b, v3.16b, v2.16b
176+
; CHECK-NEXT: neg v1.4s, v1.4s
177+
; CHECK-NEXT: ushl v1.4s, v0.4s, v1.4s
178+
; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s
179+
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
186180
; CHECK-NEXT: ret
187181
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
188182
ret <4 x i32> %f

‎test/CodeGen/AArch64/funnel-shift.ll

Lines changed: 29 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
1818
define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
1919
; CHECK-LABEL: fshl_i32:
2020
; CHECK: // %bb.0:
21-
; CHECK-NEXT: orr w9, wzr, #0x20
22-
; CHECK-NEXT: sub w9, w9, w2
21+
; CHECK-NEXT: and w9, w2, #0x1f
22+
; CHECK-NEXT: neg w9, w9
2323
; CHECK-NEXT: lsl w8, w0, w2
2424
; CHECK-NEXT: lsr w9, w1, w9
2525
; CHECK-NEXT: orr w8, w8, w9
@@ -35,26 +35,22 @@ declare i37 @llvm.fshl.i37(i37, i37, i37)
3535
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
3636
; CHECK-LABEL: fshl_i37:
3737
; CHECK: // %bb.0:
38-
; CHECK-NEXT: mov x11, #31883
39-
; CHECK-NEXT: mov w10, #37
40-
; CHECK-NEXT: movk x11, #3542, lsl #16
41-
; CHECK-NEXT: movk x11, #51366, lsl #32
42-
; CHECK-NEXT: sub x12, x10, x2
43-
; CHECK-NEXT: and x8, x2, #0x1fffffffff
44-
; CHECK-NEXT: movk x11, #56679, lsl #48
45-
; CHECK-NEXT: and x12, x12, #0x1fffffffff
46-
; CHECK-NEXT: umulh x13, x8, x11
47-
; CHECK-NEXT: umulh x11, x12, x11
48-
; CHECK-NEXT: lsr x13, x13, #5
49-
; CHECK-NEXT: lsr x11, x11, #5
50-
; CHECK-NEXT: and x9, x1, #0x1fffffffff
51-
; CHECK-NEXT: msub x8, x13, x10, x8
52-
; CHECK-NEXT: msub x10, x11, x10, x12
53-
; CHECK-NEXT: lsl x13, x0, x8
54-
; CHECK-NEXT: lsr x9, x9, x10
55-
; CHECK-NEXT: orr x9, x13, x9
56-
; CHECK-NEXT: cmp x8, #0 // =0
57-
; CHECK-NEXT: csel x0, x0, x9, eq
38+
; CHECK-NEXT: mov x10, #31883
39+
; CHECK-NEXT: movk x10, #3542, lsl #16
40+
; CHECK-NEXT: movk x10, #51366, lsl #32
41+
; CHECK-NEXT: and x9, x2, #0x1fffffffff
42+
; CHECK-NEXT: movk x10, #56679, lsl #48
43+
; CHECK-NEXT: umulh x10, x9, x10
44+
; CHECK-NEXT: mov w11, #37
45+
; CHECK-NEXT: lsr x10, x10, #5
46+
; CHECK-NEXT: msub x9, x10, x11, x9
47+
; CHECK-NEXT: and x8, x1, #0x1fffffffff
48+
; CHECK-NEXT: sub x11, x11, x9
49+
; CHECK-NEXT: lsl x10, x0, x9
50+
; CHECK-NEXT: lsr x8, x8, x11
51+
; CHECK-NEXT: orr x8, x10, x8
52+
; CHECK-NEXT: cmp x9, #0 // =0
53+
; CHECK-NEXT: csel x0, x0, x8, eq
5854
; CHECK-NEXT: ret
5955
%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
6056
ret i37 %f
@@ -150,8 +146,8 @@ define i8 @fshl_i8_const_fold() {
150146
define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
151147
; CHECK-LABEL: fshr_i32:
152148
; CHECK: // %bb.0:
153-
; CHECK-NEXT: orr w9, wzr, #0x20
154-
; CHECK-NEXT: sub w9, w9, w2
149+
; CHECK-NEXT: and w9, w2, #0x1f
150+
; CHECK-NEXT: neg w9, w9
155151
; CHECK-NEXT: lsr w8, w1, w2
156152
; CHECK-NEXT: lsl w9, w0, w9
157153
; CHECK-NEXT: orr w8, w9, w8
@@ -167,21 +163,17 @@ declare i37 @llvm.fshr.i37(i37, i37, i37)
167163
define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
168164
; CHECK-LABEL: fshr_i37:
169165
; CHECK: // %bb.0:
170-
; CHECK-NEXT: mov x11, #31883
171-
; CHECK-NEXT: mov w10, #37
172-
; CHECK-NEXT: movk x11, #3542, lsl #16
173-
; CHECK-NEXT: movk x11, #51366, lsl #32
174-
; CHECK-NEXT: sub x12, x10, x2
166+
; CHECK-NEXT: mov x10, #31883
167+
; CHECK-NEXT: movk x10, #3542, lsl #16
168+
; CHECK-NEXT: movk x10, #51366, lsl #32
175169
; CHECK-NEXT: and x9, x2, #0x1fffffffff
176-
; CHECK-NEXT: movk x11, #56679, lsl #48
177-
; CHECK-NEXT: and x12, x12, #0x1fffffffff
178-
; CHECK-NEXT: umulh x13, x9, x11
179-
; CHECK-NEXT: umulh x11, x12, x11
180-
; CHECK-NEXT: lsr x13, x13, #5
181-
; CHECK-NEXT: lsr x11, x11, #5
170+
; CHECK-NEXT: movk x10, #56679, lsl #48
171+
; CHECK-NEXT: umulh x10, x9, x10
172+
; CHECK-NEXT: mov w11, #37
173+
; CHECK-NEXT: lsr x10, x10, #5
174+
; CHECK-NEXT: msub x9, x10, x11, x9
182175
; CHECK-NEXT: and x8, x1, #0x1fffffffff
183-
; CHECK-NEXT: msub x9, x13, x10, x9
184-
; CHECK-NEXT: msub x10, x11, x10, x12
176+
; CHECK-NEXT: sub x10, x11, x9
185177
; CHECK-NEXT: lsr x8, x8, x9
186178
; CHECK-NEXT: lsl x10, x0, x10
187179
; CHECK-NEXT: orr x8, x10, x8

‎test/CodeGen/PowerPC/funnel-shift-rot.ll

Lines changed: 14 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ define i64 @rotl_i64_const_shift(i64 %x) {
4040
define i16 @rotl_i16(i16 %x, i16 %z) {
4141
; CHECK-LABEL: rotl_i16:
4242
; CHECK: # %bb.0:
43-
; CHECK-NEXT: subfic 5, 4, 16
43+
; CHECK-NEXT: neg 5, 4
4444
; CHECK-NEXT: clrlwi 6, 3, 16
4545
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
4646
; CHECK-NEXT: clrlwi 5, 5, 28
@@ -75,13 +75,11 @@ define i64 @rotl_i64(i64 %x, i64 %z) {
7575
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
7676
; CHECK-LABEL: rotl_v4i32:
7777
; CHECK: # %bb.0:
78-
; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha
79-
; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l
80-
; CHECK-NEXT: lvx 4, 0, 3
81-
; CHECK-NEXT: vsubuwm 4, 4, 3
82-
; CHECK-NEXT: vslw 3, 2, 3
83-
; CHECK-NEXT: vsrw 2, 2, 4
84-
; CHECK-NEXT: xxlor 34, 35, 34
78+
; CHECK-NEXT: xxlxor 36, 36, 36
79+
; CHECK-NEXT: vslw 5, 2, 3
80+
; CHECK-NEXT: vsubuwm 3, 4, 3
81+
; CHECK-NEXT: vsrw 2, 2, 3
82+
; CHECK-NEXT: xxlor 34, 37, 34
8583
; CHECK-NEXT: blr
8684
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
8785
ret <4 x i32> %f
@@ -131,7 +129,7 @@ define i32 @rotr_i32_const_shift(i32 %x) {
131129
define i16 @rotr_i16(i16 %x, i16 %z) {
132130
; CHECK-LABEL: rotr_i16:
133131
; CHECK: # %bb.0:
134-
; CHECK-NEXT: subfic 5, 4, 16
132+
; CHECK-NEXT: neg 5, 4
135133
; CHECK-NEXT: clrlwi 6, 3, 16
136134
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
137135
; CHECK-NEXT: clrlwi 5, 5, 28
@@ -146,7 +144,7 @@ define i16 @rotr_i16(i16 %x, i16 %z) {
146144
define i32 @rotr_i32(i32 %x, i32 %z) {
147145
; CHECK-LABEL: rotr_i32:
148146
; CHECK: # %bb.0:
149-
; CHECK-NEXT: subfic 4, 4, 32
147+
; CHECK-NEXT: neg 4, 4
150148
; CHECK-NEXT: clrlwi 4, 4, 27
151149
; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
152150
; CHECK-NEXT: blr
@@ -157,7 +155,7 @@ define i32 @rotr_i32(i32 %x, i32 %z) {
157155
define i64 @rotr_i64(i64 %x, i64 %z) {
158156
; CHECK-LABEL: rotr_i64:
159157
; CHECK: # %bb.0:
160-
; CHECK-NEXT: subfic 4, 4, 64
158+
; CHECK-NEXT: neg 4, 4
161159
; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31
162160
; CHECK-NEXT: rotld 3, 3, 4
163161
; CHECK-NEXT: blr
@@ -170,13 +168,11 @@ define i64 @rotr_i64(i64 %x, i64 %z) {
170168
define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
171169
; CHECK-LABEL: rotr_v4i32:
172170
; CHECK: # %bb.0:
173-
; CHECK-NEXT: addis 3, 2, .LCPI12_0@toc@ha
174-
; CHECK-NEXT: addi 3, 3, .LCPI12_0@toc@l
175-
; CHECK-NEXT: lvx 4, 0, 3
176-
; CHECK-NEXT: vsubuwm 4, 4, 3
177-
; CHECK-NEXT: vsrw 3, 2, 3
178-
; CHECK-NEXT: vslw 2, 2, 4
179-
; CHECK-NEXT: xxlor 34, 34, 35
171+
; CHECK-NEXT: xxlxor 36, 36, 36
172+
; CHECK-NEXT: vsrw 5, 2, 3
173+
; CHECK-NEXT: vsubuwm 3, 4, 3
174+
; CHECK-NEXT: vslw 2, 2, 3
175+
; CHECK-NEXT: xxlor 34, 34, 37
180176
; CHECK-NEXT: blr
181177
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
182178
ret <4 x i32> %f

0 commit comments

Comments
 (0)