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[x86] add tests for maxnum/minnum intrinsics with nnan; NFC
Clang 6.0 was updated to create these intrinsics rather than libcalls or fcmp/select, but the backend wasn't prepared to handle that optimally. This bug is not the primary reason for PR37403: https://bugs.llvm.org/show_bug.cgi?id=37403 ...but it's probably more important for x86 perf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331988 91177308-0d34-0410-b5e6-96231b3b80d8
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‎test/CodeGen/X86/fmaxnum.ll

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -285,3 +285,101 @@ define <8 x double> @test_intrinsic_fmax_v8f64(<8 x double> %x, <8 x double> %y)
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ret <8 x double> %z
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}
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; FIXME: The IR-level FMF should propagate to the node.
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define double @maxnum_intrinsic_nnan_fmf_f64(double %a, double %b) {
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; SSE-LABEL: maxnum_intrinsic_nnan_fmf_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm0, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: maxsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: maxnum_intrinsic_nnan_fmf_f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxsd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%r = tail call nnan double @llvm.maxnum.f64(double %a, double %b)
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ret double %r
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}
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; FIXME: Make sure vectors work too.
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define <4 x float> @maxnum_intrinsic_nnan_fmf_f432(<4 x float> %a, <4 x float> %b) {
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; SSE-LABEL: maxnum_intrinsic_nnan_fmf_f432:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: maxps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: maxnum_intrinsic_nnan_fmf_f432:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%r = tail call nnan <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %r
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}
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; FIXME: Current (but legacy someday): a function-level attribute should also enable the fold.
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define float @maxnum_intrinsic_nnan_fmf_f32(float %a, float %b) #0 {
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; SSE-LABEL: maxnum_intrinsic_nnan_fmf_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: maxss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: maxnum_intrinsic_nnan_fmf_f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxss %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%r = tail call float @llvm.maxnum.f32(float %a, float %b)
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ret float %r
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}
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; FIXME: Make sure vectors work too.
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define <2 x double> @maxnum_intrinsic_nnan_attr_f64(<2 x double> %a, <2 x double> %b) #0 {
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; SSE-LABEL: maxnum_intrinsic_nnan_attr_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm1, %xmm2
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; SSE-NEXT: maxpd %xmm0, %xmm2
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: maxnum_intrinsic_nnan_attr_f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxpd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%r = tail call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b)
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ret <2 x double> %r
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}
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attributes #0 = { "no-nans-fp-math"="true" }
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‎test/CodeGen/X86/fminnum.ll

Lines changed: 99 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -276,3 +276,102 @@ define <8 x double> @test_intrinsic_fmin_v8f64(<8 x double> %x, <8 x double> %y)
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%z = call <8 x double> @llvm.minnum.v8f64(<8 x double> %x, <8 x double> %y) readnone
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ret <8 x double> %z
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}
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; FIXME: The IR-level FMF should propagate to the node.
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define float @minnum_intrinsic_nnan_fmf_f32(float %a, float %b) {
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; SSE-LABEL: minnum_intrinsic_nnan_fmf_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: minss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: minnum_intrinsic_nnan_fmf_f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vminss %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%r = tail call nnan float @llvm.minnum.f32(float %a, float %b)
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ret float %r
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}
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; FIXME: Make sure vectors work too.
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define <2 x double> @minnum_intrinsic_nnan_fmf_v2f64(<2 x double> %a, <2 x double> %b) {
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; SSE-LABEL: minnum_intrinsic_nnan_fmf_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm1, %xmm2
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; SSE-NEXT: minpd %xmm0, %xmm2
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: minnum_intrinsic_nnan_fmf_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vminpd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%r = tail call nnan <2 x double> @llvm.minnum.v2f64(<2 x double> %a, <2 x double> %b)
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ret <2 x double> %r
326+
}
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; FIXME: Current (but legacy someday): a function-level attribute should also enable the fold.
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define double @minnum_intrinsic_nnan_fmf_f64(double %a, double %b) #0 {
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; SSE-LABEL: minnum_intrinsic_nnan_fmf_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm0, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: minsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: minnum_intrinsic_nnan_fmf_f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vminsd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%r = tail call nnan double @llvm.minnum.f64(double %a, double %b)
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ret double %r
351+
}
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; FIXME: Make sure vectors work too.
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define <4 x float> @minnum_intrinsic_nnan_attr_v4f32(<4 x float> %a, <4 x float> %b) #0 {
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; SSE-LABEL: minnum_intrinsic_nnan_attr_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: minps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: minnum_intrinsic_nnan_attr_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vminps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%r = tail call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %r
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}
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attributes #0 = { "no-nans-fp-math"="true" }
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