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Simon Dardis
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[mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version
Previously, the 'movep' instruction was defined for microMIPS32r3 and shared that definition with microMIPS32R6. 'movep' was re-encoded for microMIPS32r6, so this patch provides the correct encoding. Secondly, correct the encoding of the 'rs' and 'rt' operands which have an instruction specific encoding for the registers those operands accept. Finally, correct the decoding of the 'dst_regs' operand which was extracting the relevant field from the instruction, but was actually extracting the field from the alreadly extracted field. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39495 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317475 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -535,7 +535,7 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
535535
uint64_t Address,
536536
const void *Decoder);
537537

538-
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
538+
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
539539
uint64_t Address,
540540
const void *Decoder);
541541

@@ -2481,10 +2481,8 @@ static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
24812481
return MCDisassembler::Success;
24822482
}
24832483

2484-
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
2484+
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
24852485
uint64_t Address, const void *Decoder) {
2486-
unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2487-
24882486
switch (RegPair) {
24892487
default:
24902488
return MCDisassembler::Fail;

‎lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1114,6 +1114,29 @@ MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
11141114
return res;
11151115
}
11161116

1117+
unsigned
1118+
MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
1119+
SmallVectorImpl<MCFixup> &Fixups,
1120+
const MCSubtargetInfo &STI) const {
1121+
assert(((OpNo == 2) || (OpNo == 3)) &&
1122+
"Unexpected OpNo for movep operand encoding!");
1123+
1124+
MCOperand Op = MI.getOperand(OpNo);
1125+
assert(Op.isReg() && "Operand of movep is not a register!");
1126+
switch (Op.getReg()) {
1127+
default:
1128+
llvm_unreachable("Unknown register for movep!");
1129+
case Mips::ZERO: return 0;
1130+
case Mips::S1: return 1;
1131+
case Mips::V0: return 2;
1132+
case Mips::V1: return 3;
1133+
case Mips::S0: return 4;
1134+
case Mips::S2: return 5;
1135+
case Mips::S3: return 6;
1136+
case Mips::S4: return 7;
1137+
}
1138+
}
1139+
11171140
unsigned
11181141
MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
11191142
SmallVectorImpl<MCFixup> &Fixups,

‎lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -252,6 +252,9 @@ class MipsMCCodeEmitter : public MCCodeEmitter {
252252
unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
253253
SmallVectorImpl<MCFixup> &Fixups,
254254
const MCSubtargetInfo &STI) const;
255+
unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
256+
SmallVectorImpl<MCFixup> &Fixups,
257+
const MCSubtargetInfo &STI) const;
255258

256259
unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
257260
SmallVectorImpl<MCFixup> &Fixups,

‎lib/Target/Mips/MicroMips32r6InstrFormats.td

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -829,6 +829,21 @@ class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
829829
let Inst{3-0} = 0b0000;
830830
}
831831

832+
class POOL16C_MOVEP16_FM_MMR6 : MicroMipsR6Inst16 {
833+
bits<3> dst_regs;
834+
bits<3> rt;
835+
bits<3> rs;
836+
837+
bits<16> Inst;
838+
839+
let Inst{15-10} = 0b010001;
840+
let Inst{9-7} = dst_regs;
841+
let Inst{6-4} = rt;
842+
let Inst{3} = rs{2};
843+
let Inst{2} = 0b1;
844+
let Inst{1-0} = rs{1-0};
845+
}
846+
832847
class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
833848
bits<3> rt;
834849
bits<3> rs;

‎lib/Target/Mips/MicroMips32r6InstrInfo.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -229,6 +229,7 @@ class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
229229
class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
230230
class LI16_MMR6_ENC : LI_FM_MM16;
231231
class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
232+
class MOVEP_MMR6_ENC : POOL16C_MOVEP16_FM_MMR6;
232233
class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
233234
class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
234235
class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
@@ -1204,6 +1205,7 @@ class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
12041205
MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
12051206
class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
12061207
MicroMipsR6Inst16;
1208+
class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMoveP>, MMR6Arch<"movep">;
12071209
class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">,
12081210
MicroMipsR6Inst16;
12091211
class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
@@ -1679,6 +1681,8 @@ def LI16_MMR6 : StdMMR6Rel, LI16_MMR6_DESC, LI16_MMR6_ENC,
16791681
ISA_MICROMIPS32R6;
16801682
def MOVE16_MMR6 : StdMMR6Rel, MOVE16_MMR6_DESC, MOVE16_MMR6_ENC,
16811683
ISA_MICROMIPS32R6;
1684+
def MOVEP_MMR6 : StdMMR6Rel, MOVEP_MMR6_DESC, MOVEP_MMR6_ENC,
1685+
ISA_MICROMIPS32R6;
16821686
def SDBBP16_MMR6 : StdMMR6Rel, SDBBP16_MMR6_DESC, SDBBP16_MMR6_ENC,
16831687
ISA_MICROMIPS32R6;
16841688
def SUBU16_MMR6 : StdMMR6Rel, SUBU16_MMR6_DESC, SUBU16_MMR6_ENC,

‎lib/Target/Mips/MicroMipsInstrInfo.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -631,7 +631,8 @@ def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
631631
def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
632632
def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
633633
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
634-
def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16;
634+
def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
635+
ISA_MICROMIPS_NOT_32R6_64R6;
635636
def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
636637
IsAsCheapAsAMove;
637638
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,

‎lib/Target/Mips/MipsRegisterInfo.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -616,6 +616,7 @@ def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> {
616616

617617
def GPRMM16OpndMoveP : RegisterOperand<GPRMM16MoveP> {
618618
let ParserMatchClass = GPRMM16AsmOperandMoveP;
619+
let EncoderMethod = "getMovePRegSingleOpValue";
619620
}
620621

621622
def GPR64Opnd : RegisterOperand<GPR64> {

‎lib/Target/Mips/MipsScheduleGeneric.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -736,6 +736,7 @@ def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP_MM$")>;
736736
def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP_MM$")>;
737737
def : InstRW<[GenericDSPShort], (instregex "^MODSUB_MM$")>;
738738
def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MM$")>;
739+
def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MMR6$")>;
739740
def : InstRW<[GenericDSPShort], (instregex "^MOVN_I_MM$")>;
740741
def : InstRW<[GenericDSPShort], (instregex "^MOVZ_I_MM$")>;
741742
def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP_MM$")>;

‎test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
0x09 0x46 # CHECK: mfhi $9
2828
0x49 0x46 # CHECK: mflo $9
2929
0x21 0x0f # CHECK: move $25, $1
30+
0x9a 0x85 # CHECK: movep $4, $21, $18, $17
3031
0xa9 0x45 # CHECK: jrc $9
3132
0xc9 0x45 # CHECK: jalr $9
3233
0xe9 0x45 # CHECK: jalrs16 $9

‎test/MC/Disassembler/Mips/micromips32r3/valid.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
2727
0x46 0x09 # CHECK: mfhi $9
2828
0x46 0x49 # CHECK: mflo $9
2929
0x0f 0x21 # CHECK: move $25, $1
30+
0x85 0x9a # CHECK: movep $4, $21, $18, $17
3031
0x45 0xa9 # CHECK: jrc $9
3132
0x45 0xc9 # CHECK: jalr $9
3233
0x45 0xe9 # CHECK: jalrs16 $9

‎test/MC/Disassembler/Mips/micromips32r6/valid.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
0x29 0x82 # CHECK: lhu16 $3, 4($16)
2222
0x09 0x94 # CHECK: lbu16 $3, 4($17)
2323
0x09 0x9f # CHECK: lbu16 $3, -1($17)
24-
0x84 0x34 # CHECK: movep $5, $6, $2, $3
24+
0x44 0x36 # CHECK: movep $5, $6, $2, $3
2525
0x04 0xcc # CHECK: addu16 $6, $17, $4
2626
0x44 0x21 # CHECK: and16 $16, $2
2727
0x2e 0x56 # CHECK: andi16 $4, $5, 8

‎test/MC/Disassembler/Mips/micromips64r6/valid.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323
0x45 0x2b # CHECK: jalr $9
2424
0x45 0x23 # CHECK: jrc16 $9
2525
0x44 0xb3 # CHECK: jrcaddiusp 20
26-
0x84 0x34 # CHECK: movep $5, $6, $2, $3
26+
0x44 0x36 # CHECK: movep $5, $6, $2, $3
2727
0x45 0xf9 # CHECK: or16 $3, $7
2828
0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
2929
0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)

‎test/MC/Mips/micromips32r6/valid.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@
8484
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
8585
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
8686
lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
87-
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
87+
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x44,0x36]
8888
rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
8989
rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
9090
rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]

‎test/MC/Mips/micromips64r6/valid.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ a:
3535
lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
3636
lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
3737
lbu16 $3, -1($17) # CHECK: lbu16 $3, -1($17) # encoding: [0x09,0x9f]
38-
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
38+
movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x44,0x36]
3939
not16 $4, $7 # CHECK: not16 $4, $7 # encoding: [0x46,0x70]
4040
or16 $3, $7 # CHECK: or16 $3, $7 # encoding: [0x45,0xf9]
4141
ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]

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