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jroelofsAlexisPerry
jroelofs
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AlexisPerry
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[llvm][AArch64] SVE2 is an optional feature in ARMv9.0a (llvm#96007)
... so move it out of the `implied_features` list, and into the `DefaultExts` list.
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‎llvm/docs/ReleaseNotes.rst

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@@ -118,6 +118,13 @@ Changes to the AArch64 Backend
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in ``standard`` being equal to ``bti+pac-ret+pc`` when ``+pauth-lr``
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is passed as part of ``-mcpu=`` options.
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* SVE and SVE2 have been moved to the default extensions list for ARMv9.0,
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making them optional per the Arm ARM. Existing v9.0+ CPUs in the backend that
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support these extensions continue to have these features enabled by default
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when specified via ``-march=`` or an ``-mcpu=`` that supports them. The
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attribute ``"target-features"="+v9a"`` no longer implies ``"+sve"`` and
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``"+sve2"`` respectively.
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Changes to the AMDGPU Backend
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-----------------------------
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‎llvm/lib/Target/AArch64/AArch64Features.td

Lines changed: 1 addition & 1 deletion
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@@ -799,7 +799,7 @@ def HasV8_9aOps : Architecture64<8, 9, "a", "v8.9a",
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!listconcat(HasV8_8aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC,
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FeatureRASv2])>;
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def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",
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[HasV8_5aOps, FeatureMEC, FeatureSVE2],
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[HasV8_5aOps, FeatureMEC],
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!listconcat(HasV8_5aOps.DefaultExts, [FeatureFullFP16, FeatureSVE,
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FeatureSVE2])>;
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def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a",

‎llvm/lib/Target/AArch64/AArch64Processors.td

Lines changed: 24 additions & 12 deletions
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@@ -690,11 +690,13 @@ def ProcessorFeatures {
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list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
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FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
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FeatureFP16FML,
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
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FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
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FeatureFP16FML,
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
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FeatureNEON, FeatureFullFP16, FeatureDotProd,
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FeatureRCPC, FeatureSSBS, FeatureRAS,
@@ -726,19 +728,23 @@ def ProcessorFeatures {
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FeatureFP16FML, FeatureSVE, FeatureTRBE,
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FeatureSVE2BitPerm, FeatureBF16, FeatureETE,
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FeaturePerfMon, FeatureMatMulInt8, FeatureSPE,
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FeatureSB, FeatureSSBS, FeatureFullFP16, FeaturePAuth, FeaturePredRes, FeatureFlagM];
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FeatureSB, FeatureSSBS, FeatureFullFP16, FeaturePAuth, FeaturePredRes, FeatureFlagM,
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FeatureSVE2];
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list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
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FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
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FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
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FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
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FeaturePerfMon, FeatureSPE, FeatureSPE_EEF,
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> A725 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
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FeatureETE, FeaturePerfMon, FeatureSPE,
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FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
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FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS];
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FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
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FeatureFP16FML, FeatureSSBS, FeaturePredRes,
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FeatureSB, FeatureRDM, FeatureDotProd,
@@ -771,16 +777,19 @@ def ProcessorFeatures {
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FeatureSPE, FeatureBF16, FeatureMatMulInt8,
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FeatureMTE, FeatureSVE2BitPerm, FeatureFullFP16,
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FeatureFP16FML,
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FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS];
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FeatureSB, FeaturePAuth, FeaturePredRes, FeatureFlagM, FeatureSSBS,
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FeatureSVE2];
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list<SubtargetFeature> X4 = [HasV9_2aOps,
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FeaturePerfMon, FeatureETE, FeatureTRBE,
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FeatureSPE, FeatureMTE, FeatureSVE2BitPerm,
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FeatureFP16FML, FeatureSPE_EEF,
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes];
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FeatureSB, FeatureSSBS, FeaturePAuth, FeatureFlagM, FeaturePredRes,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> X925 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
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FeatureETE, FeaturePerfMon, FeatureSPE,
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FeatureSVE2BitPerm, FeatureSPE_EEF, FeatureTRBE,
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FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS];
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FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
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FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
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FeatureSVE, FeatureComplxNum,
@@ -849,7 +858,8 @@ def ProcessorFeatures {
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FeatureFullFP16, FeatureMTE, FeaturePerfMon,
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FeatureRandGen, FeatureSPE, FeatureSPE_EEF,
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FeatureSVE2BitPerm,
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FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM];
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FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
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FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureFP16FML,
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FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
@@ -871,12 +881,14 @@ def ProcessorFeatures {
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FeatureFullFP16, FeatureLS64, FeatureMTE,
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FeaturePerfMon, FeatureRandGen, FeatureSPE,
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FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
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FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM];
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FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> NeoverseV3AE = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
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FeatureFullFP16, FeatureLS64, FeatureMTE,
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FeaturePerfMon, FeatureRandGen, FeatureSPE,
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FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE,
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FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM];
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FeatureSSBS, FeatureSB, FeaturePredRes, FeaturePAuth, FeatureFlagM,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
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FeatureNEON, FeatureSPE, FeaturePerfMon];
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list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,

‎llvm/unittests/TargetParser/TargetParserTest.cpp

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@@ -2473,7 +2473,7 @@ AArch64ExtensionDependenciesBaseArchTestParams
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{},
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{"v8.1a", "crc", "fp-armv8", "lse", "rdm", "neon"},
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{}},
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{AArch64::ARMV9_5A, {}, {"v9.5a", "sve", "sve2", "mops", "cpa"}, {}},
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{AArch64::ARMV9_5A, {}, {"v9.5a", "mops", "cpa"}, {}},
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// Positive modifiers
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{AArch64::ARMV8A, {"fp16"}, {"fullfp16"}, {}},

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