Skip to content

Commit 5fa58e2

Browse files
michaelmaitlandwangpc-pp
michaelmaitland
and
wangpc-pp
committed
[RISCV] Split PseudoVFADD, PseudoVFSUB, and PseudoVFRSUB by SEW
Co-authored-by: Wang Pengcheng <[email protected]>
1 parent 2a5ba4f commit 5fa58e2

File tree

6 files changed

+52
-34
lines changed

6 files changed

+52
-34
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2917,26 +2917,27 @@ multiclass VPseudoVMAX_VV_VF {
29172917

29182918
multiclass VPseudoVALU_VV_VF_RM {
29192919
foreach m = MxListF in {
2920-
defm "" : VPseudoBinaryFV_VV_RM<m>,
2921-
SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX,
2922-
forceMergeOpRead=true>;
2920+
foreach e = SchedSEWSet<m.MX, isF=1>.val in
2921+
defm "" : VPseudoBinaryFV_VV_RM<m, "", sew=e>,
2922+
SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX, e,
2923+
forceMergeOpRead=true>;
29232924
}
29242925

29252926
foreach f = FPList in {
29262927
foreach m = f.MxList in {
2927-
defm "" : VPseudoBinaryV_VF_RM<m, f>,
2928+
defm "" : VPseudoBinaryV_VF_RM<m, f, "", sew=f.SEW>,
29282929
SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,
2929-
forceMergeOpRead=true>;
2930+
f.SEW, forceMergeOpRead=true>;
29302931
}
29312932
}
29322933
}
29332934

29342935
multiclass VPseudoVALU_VF_RM {
29352936
foreach f = FPList in {
29362937
foreach m = f.MxList in {
2937-
defm "" : VPseudoBinaryV_VF_RM<m, f>,
2938+
defm "" : VPseudoBinaryV_VF_RM<m, f, "", sew=f.SEW>,
29382939
SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,
2939-
forceMergeOpRead=true>;
2940+
f.SEW, forceMergeOpRead=true>;
29402941
}
29412942
}
29422943
}
@@ -7061,11 +7062,12 @@ defm : VPatBinaryV_WV_WX_WI_RM<"int_riscv_vnclip", "PseudoVNCLIP",
70617062
//===----------------------------------------------------------------------===//
70627063
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
70637064
//===----------------------------------------------------------------------===//
7064-
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfadd", "PseudoVFADD",
7065-
AllFloatVectors>;
7066-
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfsub", "PseudoVFSUB",
7067-
AllFloatVectors>;
7068-
defm : VPatBinaryV_VX_RM<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors>;
7065+
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfadd", "PseudoVFADD", AllFloatVectors,
7066+
isSEWAware = 1>;
7067+
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfsub", "PseudoVFSUB", AllFloatVectors,
7068+
isSEWAware = 1>;
7069+
defm : VPatBinaryV_VX_RM<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors,
7070+
isSEWAware = 1>;
70697071

70707072
//===----------------------------------------------------------------------===//
70717073
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1204,9 +1204,9 @@ foreach mti = AllMasks in {
12041204
// 13. Vector Floating-Point Instructions
12051205

12061206
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
1207-
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fadd, "PseudoVFADD">;
1208-
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fsub, "PseudoVFSUB">;
1209-
defm : VPatBinaryFPSDNode_R_VF_RM<any_fsub, "PseudoVFRSUB">;
1207+
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fadd, "PseudoVFADD", isSEWAware=1>;
1208+
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fsub, "PseudoVFSUB", isSEWAware=1>;
1209+
defm : VPatBinaryFPSDNode_R_VF_RM<any_fsub, "PseudoVFRSUB", isSEWAware=1>;
12101210

12111211
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
12121212
defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF_RM<fadd, "PseudoVFWADD">;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2425,9 +2425,9 @@ foreach vtiToWti = AllWidenableIntVectors in
24252425
// 13. Vector Floating-Point Instructions
24262426

24272427
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
2428-
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fadd_vl, "PseudoVFADD">;
2429-
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fsub_vl, "PseudoVFSUB">;
2430-
defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fsub_vl, "PseudoVFRSUB">;
2428+
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fadd_vl, "PseudoVFADD", isSEWAware=1>;
2429+
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fsub_vl, "PseudoVFSUB", isSEWAware=1>;
2430+
defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fsub_vl, "PseudoVFRSUB", isSEWAware=1>;
24312431

24322432
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
24332433
defm : VPatBinaryFPWVL_VV_VF_WV_WF_RM<riscv_vfwadd_vl, riscv_vfwadd_w_vl, "PseudoVFWADD">;

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -732,12 +732,20 @@ foreach mx = SchedMxListW in {
732732
}
733733

734734
// 13. Vector Floating-Point Instructions
735+
foreach mx = SchedMxListF in {
736+
foreach sew = SchedSEWSet<mx, isF=1>.val in {
737+
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
738+
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
739+
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
740+
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
741+
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
742+
}
743+
}
744+
}
735745
foreach mx = SchedMxList in {
736746
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
737747
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
738748
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
739-
defm "" : LMULWriteResMX<"WriteVFALUV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
740-
defm "" : LMULWriteResMX<"WriteVFALUF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
741749
defm "" : LMULWriteResMX<"WriteVFMulV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
742750
defm "" : LMULWriteResMX<"WriteVFMulF", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
743751
defm "" : LMULWriteResMX<"WriteVFMulAddV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
@@ -1137,8 +1145,8 @@ defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
11371145
defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
11381146

11391147
// 14. Vector Floating-Point Instructions
1140-
defm "" : LMULReadAdvance<"ReadVFALUV", 0>;
1141-
defm "" : LMULReadAdvance<"ReadVFALUF", 0>;
1148+
defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
1149+
defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
11421150
defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
11431151
defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
11441152
defm "" : LMULReadAdvance<"ReadVFMulV", 0>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -486,12 +486,20 @@ foreach mx = SchedMxList in {
486486
}
487487

488488
// 13. Vector Floating-Point Instructions
489+
foreach mx = SchedMxListF in {
490+
foreach sew = SchedSEWSet<mx, isF=1>.val in {
491+
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
492+
defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
493+
let Latency = 6, ReleaseAtCycles = [LMulLat] in {
494+
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
495+
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
496+
}
497+
}
498+
}
489499
foreach mx = SchedMxList in {
490500
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
491501
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
492502
let Latency = 6, ReleaseAtCycles = [LMulLat] in {
493-
defm "" : LMULWriteResMX<"WriteVFALUV", [SiFiveP600VectorArith], mx, IsWorstCase>;
494-
defm "" : LMULWriteResMX<"WriteVFALUF", [SiFiveP600VectorArith], mx, IsWorstCase>;
495503
defm "" : LMULWriteResMX<"WriteVFMulV", [SiFiveP600VectorArith], mx, IsWorstCase>;
496504
defm "" : LMULWriteResMX<"WriteVFMulF", [SiFiveP600VectorArith], mx, IsWorstCase>;
497505
defm "" : LMULWriteResMX<"WriteVFMulAddV", [SiFiveP600VectorArith], mx, IsWorstCase>;
@@ -925,8 +933,8 @@ defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
925933
defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
926934

927935
// 14. Vector Floating-Point Instructions
928-
defm "" : LMULReadAdvance<"ReadVFALUV", 0>;
929-
defm "" : LMULReadAdvance<"ReadVFALUF", 0>;
936+
defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
937+
defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
930938
defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
931939
defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
932940
defm "" : LMULReadAdvance<"ReadVFMulV", 0>;

‎llvm/lib/Target/RISCV/RISCVScheduleV.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -397,8 +397,8 @@ defm "" : LMULSchedWritesW<"WriteVNClipI">;
397397

398398
// 13. Vector Floating-Point Instructions
399399
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
400-
defm "" : LMULSchedWrites<"WriteVFALUV">;
401-
defm "" : LMULSchedWrites<"WriteVFALUF">;
400+
defm "" : LMULSEWSchedWritesF<"WriteVFALUV">;
401+
defm "" : LMULSEWSchedWritesF<"WriteVFALUF">;
402402
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
403403
defm "" : LMULSchedWritesFW<"WriteVFWALUV">;
404404
defm "" : LMULSchedWritesFW<"WriteVFWALUF">;
@@ -622,8 +622,8 @@ defm "" : LMULSchedReadsW<"ReadVNClipX">;
622622

623623
// 13. Vector Floating-Point Instructions
624624
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
625-
defm "" : LMULSchedReads<"ReadVFALUV">;
626-
defm "" : LMULSchedReads<"ReadVFALUF">;
625+
defm "" : LMULSEWSchedReadsF<"ReadVFALUV">;
626+
defm "" : LMULSEWSchedReadsF<"ReadVFALUF">;
627627
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
628628
defm "" : LMULSchedReadsFW<"ReadVFWALUV">;
629629
defm "" : LMULSchedReadsFW<"ReadVFWALUF">;
@@ -868,8 +868,8 @@ defm "" : LMULWriteResW<"WriteVNClipX", []>;
868868
defm "" : LMULWriteResW<"WriteVNClipI", []>;
869869

870870
// 13. Vector Floating-Point Instructions
871-
defm "" : LMULWriteRes<"WriteVFALUV", []>;
872-
defm "" : LMULWriteRes<"WriteVFALUF", []>;
871+
defm "" : LMULSEWWriteResF<"WriteVFALUV", []>;
872+
defm "" : LMULSEWWriteResF<"WriteVFALUF", []>;
873873
defm "" : LMULWriteResFW<"WriteVFWALUV", []>;
874874
defm "" : LMULWriteResFW<"WriteVFWALUF", []>;
875875
defm "" : LMULWriteRes<"WriteVFMulV", []>;
@@ -1024,8 +1024,8 @@ defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
10241024
defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
10251025

10261026
// 13. Vector Floating-Point Instructions
1027-
defm "" : LMULReadAdvance<"ReadVFALUV", 0>;
1028-
defm "" : LMULReadAdvance<"ReadVFALUF", 0>;
1027+
defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
1028+
defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
10291029
defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
10301030
defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
10311031
defm "" : LMULReadAdvance<"ReadVFMulV", 0>;

0 commit comments

Comments
 (0)