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[InstCombine][NFC] precommit tests for signed floor division
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2 files changed

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‎llvm/test/Transforms/InstCombine/add.ll

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Original file line numberDiff line numberDiff line change
@@ -3018,6 +3018,40 @@ define i32 @floor_sdiv_wrong_op(i32 %x, i32 %y) {
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ret i32 %r
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}
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define i32 @floor_sdiv_using_srem_by_8(i32 %x) {
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; CHECK-LABEL: @floor_sdiv_using_srem_by_8(
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; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 8
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 8
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; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[R]], -2147483648
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; CHECK-NEXT: [[S:%.*]] = sext i1 [[I]] to i32
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; CHECK-NEXT: [[F:%.*]] = add nsw i32 [[D]], [[S]]
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; CHECK-NEXT: ret i32 [[F]]
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;
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%d = sdiv i32 %x, 8
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%r = srem i32 %x, 8
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%i = icmp ugt i32 %r, -2147483648
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%s = sext i1 %i to i32
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%f = add i32 %d, %s
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ret i32 %f
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}
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define i32 @floor_sdiv_using_srem_by_2(i32 %x) {
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; CHECK-LABEL: @floor_sdiv_using_srem_by_2(
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; CHECK-NEXT: [[D:%.*]] = sdiv i32 [[X:%.*]], 2
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 2
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; CHECK-NEXT: [[I:%.*]] = icmp ugt i32 [[R]], -2147483648
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; CHECK-NEXT: [[S:%.*]] = sext i1 [[I]] to i32
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; CHECK-NEXT: [[F:%.*]] = add nsw i32 [[D]], [[S]]
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; CHECK-NEXT: ret i32 [[F]]
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;
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%d = sdiv i32 %x, 2
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%r = srem i32 %x, 2
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%i = icmp ugt i32 %r, -2147483648
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%s = sext i1 %i to i32
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%f = add i32 %d, %s
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ret i32 %f
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}
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30213055
; (X s>> (BW - 1)) + (zext (X s> 0)) --> (X s>> (BW - 1)) | (zext (X != 0))
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define i8 @signum_i8_i8(i8 %x) {

‎llvm/test/Transforms/InstCombine/icmp-srem.ll

Lines changed: 146 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,146 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i1 @icmp_ugt_srem5_smin(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ugt_srem5_smin(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], -2147483648
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ugt i32 %r, -2147483648
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ret i1 %c
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}
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define i1 @icmp_ugt_srem5_m5(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ugt_srem5_m5(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], -5
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ugt i32 %r, -5
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ret i1 %c
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}
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define i1 @icmp_ugt_srem5_m4(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ugt_srem5_m4(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], -4
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ugt i32 %r, -4
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ret i1 %c
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}
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define i1 @icmp_ugt_srem5_3(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ugt_srem5_3(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], 3
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ugt i32 %r, 3
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ret i1 %c
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}
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define i1 @icmp_ugt_srem5_4(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ugt_srem5_4(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], 4
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ugt i32 %r, 4
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ret i1 %c
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}
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define i1 @icmp_ugt_srem5_smaxm1(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ugt_srem5_smaxm1(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[R]], 2147483646
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ugt i32 %r, 2147483646
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ret i1 %c
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}
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define i1 @icmp_ult_srem5_sminp1(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ult_srem5_sminp1(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], -2147483647
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ult i32 %r, -2147483647
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ret i1 %c
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}
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define i1 @icmp_ult_srem5_m4(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ult_srem5_m4(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], -4
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ult i32 %r, -4
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ret i1 %c
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}
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define i1 @icmp_ult_srem5_m3(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ult_srem5_m3(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], -3
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ult i32 %r, -3
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ret i1 %c
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}
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define i1 @icmp_ult_srem5_4(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ult_srem5_4(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], 4
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ult i32 %r, 4
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ret i1 %c
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}
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define i1 @icmp_ult_srem5_5(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ult_srem5_5(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], 5
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ult i32 %r, 5
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ret i1 %c
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}
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define i1 @icmp_ult_srem5_smax(i32 %x) {
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; CHECK-LABEL: define i1 @icmp_ult_srem5_smax(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[R:%.*]] = srem i32 [[X]], 5
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[R]], 2147483647
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; CHECK-NEXT: ret i1 [[C]]
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;
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%r = srem i32 %x, 5
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%c = icmp ult i32 %r, 2147483647
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ret i1 %c
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}

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