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Jim Grosbach
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Add ARM binary encoding information for the rest of the indexed loads.
llvm-svn: 119821
1 parent 8e0cc61 commit 003c6e7

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2 files changed

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‎llvm/lib/Target/ARM/ARMInstrFormats.td

Lines changed: 15 additions & 126 deletions
Original file line numberDiff line numberDiff line change
@@ -522,6 +522,21 @@ class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
522522
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
523523
}
524524

525+
class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
526+
IndexMode im, Format f, InstrItinClass itin, string opc,
527+
string asm, string cstr, list<dag> pattern>
528+
: I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
529+
opc, asm, cstr, pattern> {
530+
bits<4> Rt;
531+
let Inst{27-25} = 0b000;
532+
let Inst{24} = isPre; // P bit
533+
let Inst{21} = isPre; // W bit
534+
let Inst{20} = op20; // L bit
535+
let Inst{15-12} = Rt; // Rt
536+
let Inst{7-4} = op;
537+
}
538+
539+
525540
// stores
526541
class AI3sth<dag oops, dag iops, Format f, InstrItinClass itin,
527542
string opc, string asm, list<dag> pattern>
@@ -567,66 +582,6 @@ class AI3std<dag oops, dag iops, Format f, InstrItinClass itin,
567582
let Inst{27-25} = 0b000;
568583
}
569584

570-
// Pre-indexed loads
571-
class AI3ldhpr<dag oops, dag iops, Format f, InstrItinClass itin,
572-
string opc, string asm, string cstr, list<dag> pattern>
573-
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
574-
opc, asm, cstr, pattern> {
575-
let Inst{4} = 1;
576-
let Inst{5} = 1; // H bit
577-
let Inst{6} = 0; // S bit
578-
let Inst{7} = 1;
579-
let Inst{20} = 1; // L bit
580-
let Inst{21} = 1; // W bit
581-
let Inst{24} = 1; // P bit
582-
let Inst{27-25} = 0b000;
583-
}
584-
class AI3ldshpr<dag oops, dag iops, Format f, InstrItinClass itin,
585-
string opc, string asm, string cstr, list<dag> pattern>
586-
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
587-
opc, asm, cstr, pattern> {
588-
bits<14> addr;
589-
bits<4> Rt;
590-
let Inst{27-25} = 0b000;
591-
let Inst{24} = 1; // P bit
592-
let Inst{23} = addr{8}; // U bit
593-
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
594-
let Inst{21} = 1; // W bit
595-
let Inst{20} = 1; // L bit
596-
let Inst{19-16} = addr{12-9}; // Rn
597-
let Inst{15-12} = Rt; // Rt
598-
let Inst{11-8} = addr{7-4}; // imm7_4/zero
599-
let Inst{7-4} = 0b1111;
600-
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
601-
}
602-
class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
603-
string opc, string asm, string cstr, list<dag> pattern>
604-
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
605-
opc, asm, cstr, pattern> {
606-
let Inst{4} = 1;
607-
let Inst{5} = 0; // H bit
608-
let Inst{6} = 1; // S bit
609-
let Inst{7} = 1;
610-
let Inst{20} = 1; // L bit
611-
let Inst{21} = 1; // W bit
612-
let Inst{24} = 1; // P bit
613-
let Inst{27-25} = 0b000;
614-
}
615-
class AI3lddpr<dag oops, dag iops, Format f, InstrItinClass itin,
616-
string opc, string asm, string cstr, list<dag> pattern>
617-
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
618-
opc, asm, cstr, pattern> {
619-
let Inst{4} = 1;
620-
let Inst{5} = 0; // H bit
621-
let Inst{6} = 1; // S bit
622-
let Inst{7} = 1;
623-
let Inst{20} = 0; // L bit
624-
let Inst{21} = 1; // W bit
625-
let Inst{24} = 1; // P bit
626-
let Inst{27-25} = 0b000;
627-
}
628-
629-
630585
// Pre-indexed stores
631586
class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
632587
string opc, string asm, string cstr, list<dag> pattern>
@@ -655,72 +610,6 @@ class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
655610
let Inst{27-25} = 0b000;
656611
}
657612

658-
// Post-indexed loads
659-
class AI3ldhpo<dag oops, dag iops, Format f, InstrItinClass itin,
660-
string opc, string asm, string cstr, list<dag> pattern>
661-
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
662-
opc, asm, cstr,pattern> {
663-
bits<10> offset;
664-
bits<4> Rt;
665-
bits<4> Rn;
666-
let Inst{27-25} = 0b000;
667-
let Inst{24} = 0; // P bit
668-
let Inst{23} = offset{8}; // U bit
669-
let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
670-
let Inst{21} = 0; // W bit
671-
let Inst{20} = 1; // L bit
672-
let Inst{19-16} = Rn; // Rn
673-
let Inst{15-12} = Rt; // Rt
674-
let Inst{11-8} = offset{7-4}; // imm7_4/zero
675-
let Inst{7-4} = 0b1011;
676-
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
677-
}
678-
class AI3ldshpo<dag oops, dag iops, Format f, InstrItinClass itin,
679-
string opc, string asm, string cstr, list<dag> pattern>
680-
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
681-
opc, asm, cstr,pattern> {
682-
bits<10> offset;
683-
bits<4> Rt;
684-
bits<4> Rn;
685-
let Inst{27-25} = 0b000;
686-
let Inst{24} = 0; // P bit
687-
let Inst{23} = offset{8}; // U bit
688-
let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
689-
let Inst{21} = 0; // W bit
690-
let Inst{20} = 1; // L bit
691-
let Inst{19-16} = Rn; // Rn
692-
let Inst{15-12} = Rt; // Rt
693-
let Inst{11-8} = offset{7-4}; // imm7_4/zero
694-
let Inst{7-4} = 0b1111;
695-
let Inst{3-0} = offset{3-0}; // imm3_0/Rm
696-
}
697-
class AI3ldsbpo<dag oops, dag iops, Format f, InstrItinClass itin,
698-
string opc, string asm, string cstr, list<dag> pattern>
699-
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
700-
opc, asm, cstr,pattern> {
701-
let Inst{4} = 1;
702-
let Inst{5} = 0; // H bit
703-
let Inst{6} = 1; // S bit
704-
let Inst{7} = 1;
705-
let Inst{20} = 1; // L bit
706-
let Inst{21} = 0; // W bit
707-
let Inst{24} = 0; // P bit
708-
let Inst{27-25} = 0b000;
709-
}
710-
class AI3lddpo<dag oops, dag iops, Format f, InstrItinClass itin,
711-
string opc, string asm, string cstr, list<dag> pattern>
712-
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
713-
opc, asm, cstr, pattern> {
714-
let Inst{4} = 1;
715-
let Inst{5} = 0; // H bit
716-
let Inst{6} = 1; // S bit
717-
let Inst{7} = 1;
718-
let Inst{20} = 0; // L bit
719-
let Inst{21} = 0; // W bit
720-
let Inst{24} = 0; // P bit
721-
let Inst{27-25} = 0b000;
722-
}
723-
724613
// Post-indexed stores
725614
class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
726615
string opc, string asm, string cstr, list<dag> pattern>

‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 48 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -1586,6 +1586,7 @@ def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
15861586
(ins addrmode3:$addr), LdMiscFrm,
15871587
IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
15881588
[]>, Requires<[IsARM, HasV5TE]>;
1589+
}
15891590

15901591
// Indexed loads
15911592
multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
@@ -1618,80 +1619,78 @@ multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
16181619
}
16191620
}
16201621

1622+
let mayLoad = 1, neverHasSideEffects = 1 in {
16211623
defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
16221624
defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1625+
}
16231626

1624-
def LDRH_PRE : AI3ldhpr<(outs GPR:$Rt, GPR:$Rn_wb),
1625-
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1626-
"ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1627-
1628-
def LDRH_POST : AI3ldhpo<(outs GPR:$Rt, GPR:$Rn_wb),
1629-
(ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1630-
"ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
1631-
1632-
def LDRSH_PRE : AI3ldshpr<(outs GPR:$Rt, GPR:$Rn_wb),
1633-
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1634-
"ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1635-
1636-
def LDRSH_POST: AI3ldshpo<(outs GPR:$Rt, GPR:$Rn_wb),
1637-
(ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1638-
"ldrsh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
1639-
1640-
def LDRSB_PRE : AI3ldsbpr<(outs GPR:$Rt, GPR:$Rn_wb),
1641-
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
1642-
"ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
1643-
1644-
def LDRSB_POST: AI3ldsbpo<(outs GPR:$Rt, GPR:$Rn_wb),
1645-
(ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
1646-
"ldrsb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
1647-
1648-
// For disassembly only
1649-
def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1650-
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_d_ru,
1651-
"ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>,
1652-
Requires<[IsARM, HasV5TE]>;
1653-
1654-
// For disassembly only
1655-
def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
1656-
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_d_ru,
1657-
"ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>,
1658-
Requires<[IsARM, HasV5TE]>;
1627+
multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1628+
def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1629+
(ins addrmode3:$addr), IndexModePre,
1630+
LdMiscFrm, itin,
1631+
opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1632+
bits<14> addr;
1633+
let Inst{23} = addr{8}; // U bit
1634+
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1635+
let Inst{19-16} = addr{12-9}; // Rn
1636+
let Inst{11-8} = addr{7-4}; // imm7_4/zero
1637+
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1638+
}
1639+
def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1640+
(ins GPR:$Rn, am3offset:$offset), IndexModePost,
1641+
LdMiscFrm, itin,
1642+
opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1643+
bits<10> addr;
1644+
bits<4> Rn;
1645+
let Inst{23} = addr{8}; // U bit
1646+
let Inst{22} = addr{9}; // 1 == imm8, 0 == Rm
1647+
let Inst{19-16} = Rn;
1648+
let Inst{11-8} = addr{7-4}; // imm7_4/zero
1649+
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1650+
}
1651+
}
16591652

1660-
} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1653+
let mayLoad = 1, neverHasSideEffects = 1 in {
1654+
defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1655+
defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1656+
defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1657+
let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1658+
defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1659+
} // mayLoad = 1, neverHasSideEffects = 1
16611660

16621661
// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1663-
1662+
let mayLoad = 1, neverHasSideEffects = 1 in {
16641663
def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
16651664
(ins GPR:$base, am2offset:$offset), IndexModeNone,
16661665
LdFrm, IIC_iLoad_ru,
16671666
"ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
16681667
let Inst{21} = 1; // overwrite
16691668
}
1670-
16711669
def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1672-
(ins GPR:$base,am2offset:$offset), IndexModeNone,
1670+
(ins GPR:$base, am2offset:$offset), IndexModeNone,
16731671
LdFrm, IIC_iLoad_bh_ru,
16741672
"ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
16751673
let Inst{21} = 1; // overwrite
16761674
}
1677-
1678-
def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
1679-
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1675+
def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1676+
(ins GPR:$base, am3offset:$offset), IndexModePost,
1677+
LdMiscFrm, IIC_iLoad_bh_ru,
16801678
"ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
16811679
let Inst{21} = 1; // overwrite
16821680
}
1683-
1684-
def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
1685-
(ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1686-
"ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1681+
def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1682+
(ins GPR:$base, am3offset:$offset), IndexModePost,
1683+
LdMiscFrm, IIC_iLoad_bh_ru,
1684+
"ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
16871685
let Inst{21} = 1; // overwrite
16881686
}
1689-
1690-
def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
1691-
(ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
1687+
def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1688+
(ins GPR:$base, am3offset:$offset), IndexModePost,
1689+
LdMiscFrm, IIC_iLoad_bh_ru,
16921690
"ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
16931691
let Inst{21} = 1; // overwrite
16941692
}
1693+
}
16951694

16961695
// Store
16971696

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