[AArch64][GlobalISel] Fix crash during G_SHUFFLE_VECTOR legalization.

A new widening rule was running before the shuffle was canonicalized into a
homogenous form. Moving the rules around to ensure it's done before the
widening fixes the crash, although this particular test still falls back.

Author: aemerson

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -956,18 +956,18 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
           },
           changeTo(1, 0))
       .moreElementsToNextPow2(0)
-      .widenScalarOrEltToNextPow2OrMinSize(0, 8)
-      .clampNumElements(0, v8s8, v16s8)
-      .clampNumElements(0, v4s16, v8s16)
-      .clampNumElements(0, v4s32, v4s32)
-      .clampNumElements(0, v2s64, v2s64)
       .moreElementsIf(
           [](const LegalityQuery &Query) {
             return Query.Types[0].isVector() && Query.Types[1].isVector() &&
                    Query.Types[0].getNumElements() <
                        Query.Types[1].getNumElements();
           },
-          changeTo(0, 1));
+          changeTo(0, 1))
+      .widenScalarOrEltToNextPow2OrMinSize(0, 8)
+      .clampNumElements(0, v8s8, v16s8)
+      .clampNumElements(0, v4s16, v8s16)
+      .clampNumElements(0, v4s32, v4s32)
+      .clampNumElements(0, v2s64, v2s64);
 
   getActionDefinitionsBuilder(G_CONCAT_VECTORS)
       .legalFor({{v4s32, v2s32}, {v8s16, v4s16}, {v16s8, v8s8}});

llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector-widen-crash.ll

@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -global-isel-abort=2 -global-isel -o - %s | FileCheck %s
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-macosx11.0.0"
+
+declare i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32>) #0
+
+; This test currently falls back but ensures we don't crash.
+
+define i32 @bar() {
+; CHECK-LABEL: bar:
+; CHECK:       ; %bb.0: ; %bb
+; CHECK-NEXT:    movi.2d v0, #0000000000000000
+; CHECK-NEXT:    addv.4s s0, v0
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    ret
+bb:
+  %shufflevector = shufflevector <8 x i1> zeroinitializer, <8 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %zext = zext <4 x i1> %shufflevector to <4 x i32>
+  %call = call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %zext)
+  %icmp = icmp eq i32 %call, 0
+  br i1 %icmp, label %bb1, label %bb2
+
+bb1:                                              ; preds = %bb2, %bb
+  ret i32 %call
+
+bb2:                                              ; preds = %bb
+  %sext = sext i32 0 to i64
+  br label %bb1
+}
+
+attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }