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[DAG] canCreateUndefOrPoison – mark fneg/fadd/fsub/fmul/fdiv/frem as not poison generating (#142345)
After revisiting the LLVM Language Reference Manual, it is confirmed that plain floating-point operations (`fneg`, `fadd`, `fsub`, `fmul`, `fdiv`, and `frem`) propagate poison but do not inherently create new poison values. Thus, `SelectionDAG::canCreateUndefOrPoison` should return `false` for these operations by default. Poison generation in FP instructions occurs only when specific fast-math flags (`nnan`, `ninf`, or the collective fast) are present, as these flags explicitly convert NaN or Inf results into poison. References: - [`fneg` instruction documentation](https://llvm.org/docs/LangRef.html#fneg-instruction) - [`fadd` instruction documentation](https://llvm.org/docs/LangRef.html#fadd-instruction) - [`fsub` instruction documentation](https://llvm.org/docs/LangRef.html#fsub-instruction) - [`fmul` instruction documentation](https://llvm.org/docs/LangRef.html#fmul-instruction) - [`fdiv` instruction documentation](https://llvm.org/docs/LangRef.html#fdiv-instruction) - [`frem` instruction documentation](https://llvm.org/docs/LangRef.html#frem-instruction) - [Fast-Math Flags documentation](https://llvm.org/docs/LangRef.html#fast-math-flags)
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‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

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@@ -5639,6 +5639,12 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::FNEG:
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FDIV:
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case ISD::FREM:
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// No poison except from flags (which is handled above)
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return false;
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‎llvm/test/CodeGen/AMDGPU/freeze-binary.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck %s
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define float @freeze_fneg(float %input) nounwind {
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; CHECK-LABEL: freeze_fneg:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = fneg reassoc nsz arcp contract afn float %input
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%y = freeze float %x
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%z = fneg reassoc nsz arcp contract afn float %y
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ret float %z
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}
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define float @freeze_fadd(float %input) nounwind {
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; CHECK-LABEL: freeze_fadd:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_add_f32_e32 v0, 2.0, v0
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = fadd reassoc nsz arcp contract afn float %input, 1.000000e+00
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%y = freeze float %x
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%z = fadd reassoc nsz arcp contract afn float %y, 1.000000e+00
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ret float %z
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}
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define <4 x float> @freeze_fadd_vec(<4 x float> %input) nounwind {
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; CHECK-LABEL: freeze_fadd_vec:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_dual_add_f32 v0, 0x40a00000, v0 :: v_dual_add_f32 v1, 0x40a00000, v1
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; CHECK-NEXT: v_dual_add_f32 v2, 0x40a00000, v2 :: v_dual_add_f32 v3, 0x40a00000, v3
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = fadd reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
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%y = freeze <4 x float> %x
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%z = fadd reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
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ret <4 x float> %z
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}
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define float @freeze_fsub(float %input) nounwind {
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; CHECK-LABEL: freeze_fsub:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; CHECK-NEXT: v_subrev_f32_e32 v0, 1.0, v0
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = fsub reassoc nsz arcp contract afn float %input, 1.000000e+00
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%y = freeze float %x
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%z = fsub reassoc nsz arcp contract afn float %y, 1.000000e+00
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ret float %z
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}
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define <4 x float> @freeze_fsub_vec(<4 x float> %input) nounwind {
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; CHECK-LABEL: freeze_fsub_vec:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_dual_add_f32 v0, 0xc0a00000, v0 :: v_dual_add_f32 v1, 0xc0a00000, v1
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; CHECK-NEXT: v_dual_add_f32 v2, 0xc0a00000, v2 :: v_dual_add_f32 v3, 0xc0a00000, v3
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = fsub reassoc nsz arcp contract afn <4 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
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%y = freeze <4 x float> %x
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%z = fsub reassoc nsz arcp contract afn <4 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
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ret <4 x float> %z
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}
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define float @freeze_fmul(float %input) nounwind {
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; CHECK-LABEL: freeze_fmul:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mul_f32_e32 v0, 4.0, v0
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = fmul reassoc nsz arcp contract afn float %input, 2.000000e+00
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%y = freeze float %x
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%z = fmul reassoc nsz arcp contract afn float %y, 2.000000e+00
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ret float %z
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}
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define <8 x float> @freeze_fmul_vec(<8 x float> %input) nounwind {
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; CHECK-LABEL: freeze_fmul_vec:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_dual_mul_f32 v0, 4.0, v0 :: v_dual_mul_f32 v1, 0x40c00000, v1
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; CHECK-NEXT: v_dual_mul_f32 v2, 0x40c00000, v2 :: v_dual_mul_f32 v3, 4.0, v3
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; CHECK-NEXT: v_dual_mul_f32 v4, 4.0, v4 :: v_dual_mul_f32 v5, 0x40c00000, v5
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; CHECK-NEXT: v_dual_mul_f32 v6, 0x40c00000, v6 :: v_dual_mul_f32 v7, 4.0, v7
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = fmul reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
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%y = freeze <8 x float> %x
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%z = fmul reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
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ret <8 x float> %z
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}
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define float @freeze_fdiv(float %input) nounwind {
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; CHECK-LABEL: freeze_fdiv:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = fdiv reassoc nsz arcp contract afn float %input, 2.000000e+00
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%y = freeze float %x
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%z = fdiv reassoc nsz arcp contract afn float %y, 2.000000e+00
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ret float %z
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}
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define <8 x float> @freeze_fdiv_vec(<8 x float> %input) nounwind {
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; CHECK-LABEL: freeze_fdiv_vec:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_dual_mul_f32 v3, 0x3e800000, v3 :: v_dual_mul_f32 v4, 0x3e800000, v4
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; CHECK-NEXT: v_dual_mul_f32 v0, 0x3e800000, v0 :: v_dual_mul_f32 v7, 0x3e800000, v7
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; CHECK-NEXT: v_dual_mul_f32 v1, 0x3e2aaaab, v1 :: v_dual_mul_f32 v2, 0x3e2aaaab, v2
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; CHECK-NEXT: v_dual_mul_f32 v5, 0x3e2aaaab, v5 :: v_dual_mul_f32 v6, 0x3e2aaaab, v6
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = fdiv reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
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%y = freeze <8 x float> %x
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%z = fdiv reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
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ret <8 x float> %z
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}
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define float @freeze_frem(float %input) nounwind {
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; CHECK-LABEL: freeze_frem:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-NEXT: v_trunc_f32_e32 v1, v1
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; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-NEXT: v_mul_f32_e32 v1, 0.5, v0
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; CHECK-NEXT: v_trunc_f32_e32 v1, v1
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; CHECK-NEXT: v_fmac_f32_e32 v0, -2.0, v1
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = frem reassoc nsz arcp contract afn float %input, 2.000000e+00
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%y = freeze float %x
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%z = frem reassoc nsz arcp contract afn float %y, 2.000000e+00
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ret float %z
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}
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define <8 x float> @freeze_frem_vec(<8 x float> %input) nounwind {
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; CHECK-LABEL: freeze_frem_vec:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_dual_mul_f32 v8, 0x3e800000, v4 :: v_dual_mul_f32 v9, 0x3e800000, v3
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; CHECK-NEXT: v_trunc_f32_e32 v11, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
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; CHECK-NEXT: v_trunc_f32_e32 v8, v8
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; CHECK-NEXT: v_trunc_f32_e32 v9, v9
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; CHECK-NEXT: v_mul_f32_e32 v10, 0.5, v6
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
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; CHECK-NEXT: v_dual_sub_f32 v0, v0, v11 :: v_dual_mul_f32 v11, 0x3eaaaaab, v5
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; CHECK-NEXT: v_dual_fmac_f32 v4, -4.0, v8 :: v_dual_fmac_f32 v3, -4.0, v9
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; CHECK-NEXT: v_trunc_f32_e32 v10, v10
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; CHECK-NEXT: v_trunc_f32_e32 v9, v7
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; CHECK-NEXT: v_dual_fmac_f32 v6, -2.0, v10 :: v_dual_sub_f32 v7, v7, v9
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; CHECK-NEXT: v_mul_f32_e32 v8, 0.5, v1
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; CHECK-NEXT: v_trunc_f32_e32 v9, v11
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
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; CHECK-NEXT: v_mul_f32_e32 v11, 0x3e800000, v7
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; CHECK-NEXT: v_trunc_f32_e32 v8, v8
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
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; CHECK-NEXT: v_fmac_f32_e32 v1, -2.0, v8
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; CHECK-NEXT: v_fmac_f32_e32 v5, 0xc0400000, v9
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; CHECK-NEXT: v_mul_f32_e32 v10, 0x3eaaaaab, v2
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; CHECK-NEXT: v_mul_f32_e32 v12, 0x3e800000, v0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; CHECK-NEXT: v_trunc_f32_e32 v8, v10
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; CHECK-NEXT: v_trunc_f32_e32 v10, v12
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
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; CHECK-NEXT: v_fmac_f32_e32 v2, 0xc0400000, v8
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; CHECK-NEXT: v_trunc_f32_e32 v8, v11
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; CHECK-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v1
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; CHECK-NEXT: v_dual_fmac_f32 v0, -4.0, v10 :: v_dual_mul_f32 v11, 0.5, v5
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
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; CHECK-NEXT: v_fmac_f32_e32 v7, -4.0, v8
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; CHECK-NEXT: v_trunc_f32_e32 v9, v12
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; CHECK-NEXT: v_mul_f32_e32 v12, 0x3eaaaaab, v6
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
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; CHECK-NEXT: v_fmac_f32_e32 v1, 0xc0400000, v9
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; CHECK-NEXT: v_trunc_f32_e32 v9, v11
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; CHECK-NEXT: v_trunc_f32_e32 v11, v3
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; CHECK-NEXT: v_dual_mul_f32 v10, 0.5, v2 :: v_dual_fmac_f32 v5, -2.0, v9
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; CHECK-NEXT: v_sub_f32_e32 v3, v3, v11
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; CHECK-NEXT: v_trunc_f32_e32 v8, v10
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; CHECK-NEXT: v_trunc_f32_e32 v10, v12
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; CHECK-NEXT: v_trunc_f32_e32 v12, v4
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
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; CHECK-NEXT: v_fmac_f32_e32 v2, -2.0, v8
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; CHECK-NEXT: v_fmac_f32_e32 v6, 0xc0400000, v10
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3)
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; CHECK-NEXT: v_sub_f32_e32 v4, v4, v12
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%x = frem reassoc nsz arcp contract afn <8 x float> %input, <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00>
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%y = freeze <8 x float> %x
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%z = frem reassoc nsz arcp contract afn <8 x float> %y, <float 4.000000e+00, float 3.000000e+00, float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
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ret <8 x float> %z
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}

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