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[VPlan] Handle ForceTargetInstructionCost in during precomputeCosts.
Make sure ForceTargetInstruction is respected in precomputeCosts.
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3 files changed

+262
-1
lines changed

3 files changed

+262
-1
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7091,6 +7091,8 @@ void LoopVectorizationPlanner::plan(ElementCount UserVF, unsigned UserIC) {
70917091

70927092
InstructionCost VPCostContext::getLegacyCost(Instruction *UI,
70937093
ElementCount VF) const {
7094+
if (ForceTargetInstructionCost.getNumOccurrences())
7095+
return InstructionCost(ForceTargetInstructionCost.getNumOccurrences());
70947096
return CM.getInstructionCost(UI, VF);
70957097
}
70967098

@@ -7194,6 +7196,9 @@ LoopVectorizationPlanner::precomputeCosts(VPlan &Plan, ElementCount VF,
71947196
// for now.
71957197
// TODO: Switch to costing based on VPlan once the logic has been ported.
71967198
for (const auto &[RedPhi, RdxDesc] : Legal->getReductionVars()) {
7199+
if (ForceTargetInstructionCost.getNumOccurrences())
7200+
continue;
7201+
71977202
if (!CM.isInLoopReduction(RedPhi) &&
71987203
!RecurrenceDescriptor::isAnyOfRecurrenceKind(
71997204
RdxDesc.getRecurrenceKind()))

‎llvm/lib/Transforms/Vectorize/VPlan.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@ using namespace llvm::VPlanPatternMatch;
5555
namespace llvm {
5656
extern cl::opt<bool> EnableVPlanNativePath;
5757
}
58+
extern cl::opt<unsigned> ForceTargetInstructionCost;
5859

5960
static cl::opt<bool> PrintVPlansInDotFormat(
6061
"vplan-print-in-dot-format", cl::Hidden,
@@ -795,7 +796,9 @@ InstructionCost VPRegionBlock::cost(ElementCount VF, VPCostContext &Ctx) {
795796
for (VPBlockBase *Block : vp_depth_first_shallow(getEntry()))
796797
Cost += Block->cost(VF, Ctx);
797798
InstructionCost BackedgeCost =
798-
Ctx.TTI.getCFInstrCost(Instruction::Br, TTI::TCK_RecipThroughput);
799+
ForceTargetInstructionCost.getNumOccurrences()
800+
? InstructionCost(ForceTargetInstructionCost.getNumOccurrences())
801+
: Ctx.TTI.getCFInstrCost(Instruction::Br, TTI::TCK_RecipThroughput);
799802
LLVM_DEBUG(dbgs() << "Cost of " << BackedgeCost << " for VF " << VF
800803
<< ": vector loop backedge\n");
801804
Cost += BackedgeCost;

‎llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll

Lines changed: 253 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,253 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -p loop-vectorize -force-target-instruction-cost=1 -S %s | FileCheck %s
3+
4+
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128-Fn32"
5+
target triple = "arm64-apple-macosx14.0.0"
6+
7+
define double @test_reduction_costs() {
8+
; CHECK-LABEL: define double @test_reduction_costs() {
9+
; CHECK-NEXT: [[ENTRY:.*]]:
10+
; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
11+
; CHECK: [[VECTOR_PH]]:
12+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
13+
; CHECK: [[VECTOR_BODY]]:
14+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
15+
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi double [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP0:%.*]], %[[VECTOR_BODY]] ]
16+
; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi double [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP1:%.*]], %[[VECTOR_BODY]] ]
17+
; CHECK-NEXT: [[TMP0]] = call double @llvm.vector.reduce.fadd.v2f64(double [[VEC_PHI]], <2 x double> <double 3.000000e+00, double 3.000000e+00>)
18+
; CHECK-NEXT: [[TMP1]] = call double @llvm.vector.reduce.fadd.v2f64(double [[VEC_PHI1]], <2 x double> <double 9.000000e+00, double 9.000000e+00>)
19+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
20+
; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
21+
; CHECK: [[MIDDLE_BLOCK]]:
22+
; CHECK-NEXT: br i1 true, label %[[EXIT:.*]], label %[[SCALAR_PH]]
23+
; CHECK: [[SCALAR_PH]]:
24+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 2, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
25+
; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi double [ [[TMP0]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
26+
; CHECK-NEXT: [[BC_MERGE_RDX2:%.*]] = phi double [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 0.000000e+00, %[[ENTRY]] ]
27+
; CHECK-NEXT: br label %[[LOOP_1:.*]]
28+
; CHECK: [[LOOP_1]]:
29+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_1]] ]
30+
; CHECK-NEXT: [[R_1:%.*]] = phi double [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[R_1_NEXT:%.*]], %[[LOOP_1]] ]
31+
; CHECK-NEXT: [[R_2:%.*]] = phi double [ [[BC_MERGE_RDX2]], %[[SCALAR_PH]] ], [ [[R_2_NEXT:%.*]], %[[LOOP_1]] ]
32+
; CHECK-NEXT: [[R_1_NEXT]] = fadd double [[R_1]], 3.000000e+00
33+
; CHECK-NEXT: [[R_2_NEXT]] = fadd double [[R_2]], 9.000000e+00
34+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
35+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1
36+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_1]], !llvm.loop [[LOOP3:![0-9]+]]
37+
; CHECK: [[EXIT]]:
38+
; CHECK-NEXT: [[R_1_NEXT_LCSSA:%.*]] = phi double [ [[R_1_NEXT]], %[[LOOP_1]] ], [ [[TMP0]], %[[MIDDLE_BLOCK]] ]
39+
; CHECK-NEXT: [[R_2_NEXT_LCSSA:%.*]] = phi double [ [[R_2_NEXT]], %[[LOOP_1]] ], [ [[TMP1]], %[[MIDDLE_BLOCK]] ]
40+
; CHECK-NEXT: [[DIV:%.*]] = fmul double [[R_1_NEXT_LCSSA]], [[R_2_NEXT_LCSSA]]
41+
; CHECK-NEXT: ret double [[DIV]]
42+
;
43+
entry:
44+
br label %loop.1
45+
46+
loop.1:
47+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.1 ]
48+
%r.1 = phi double [ 0.000000e+00, %entry ], [ %r.1.next, %loop.1 ]
49+
%r.2 = phi double [ 0.000000e+00, %entry ], [ %r.2.next, %loop.1 ]
50+
%r.1.next = fadd double %r.1, 3.000000e+00
51+
%r.2.next = fadd double %r.2, 9.000000e+00
52+
%iv.next = add i64 %iv, 1
53+
%ec = icmp eq i64 %iv, 1
54+
br i1 %ec, label %exit, label %loop.1
55+
56+
exit:
57+
%div = fmul double %r.1.next, %r.2.next
58+
ret double %div
59+
}
60+
61+
define void @test_iv_cost(ptr %ptr.start, i8 %a, i64 %b) {
62+
; CHECK-LABEL: define void @test_iv_cost(
63+
; CHECK-SAME: ptr [[PTR_START:%.*]], i8 [[A:%.*]], i64 [[B:%.*]]) {
64+
; CHECK-NEXT: [[ENTRY:.*:]]
65+
; CHECK-NEXT: [[A_EXT:%.*]] = zext i8 [[A]] to i64
66+
; CHECK-NEXT: [[START:%.*]] = call i64 @llvm.umin.i64(i64 [[B]], i64 [[A_EXT]])
67+
; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[START]], 0
68+
; CHECK-NEXT: br i1 [[C]], label %[[EXIT:.*]], label %[[ITER_CHECK:.*]]
69+
; CHECK: [[ITER_CHECK]]:
70+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[START]], 8
71+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
72+
; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
73+
; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[START]], 32
74+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
75+
; CHECK: [[VECTOR_PH]]:
76+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[START]], 32
77+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[START]], [[N_MOD_VF]]
78+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
79+
; CHECK: [[VECTOR_BODY]]:
80+
; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
81+
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX1]], 0
82+
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX1]], 16
83+
; CHECK-NEXT: [[NEXT_GEP1:%.*]] = getelementptr i8, ptr [[PTR_START]], i64 [[TMP5]]
84+
; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[NEXT_GEP1]], i32 0
85+
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[NEXT_GEP1]], i32 16
86+
; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[TMP6]], align 1
87+
; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr [[TMP3]], align 1
88+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX1]], 32
89+
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
90+
; CHECK-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
91+
; CHECK: [[MIDDLE_BLOCK]]:
92+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[START]], [[N_VEC]]
93+
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
94+
; CHECK: [[VEC_EPILOG_ITER_CHECK]]:
95+
; CHECK-NEXT: [[IND_END6:%.*]] = getelementptr i8, ptr [[PTR_START]], i64 [[N_VEC]]
96+
; CHECK-NEXT: [[IND_END:%.*]] = sub i64 [[START]], [[N_VEC]]
97+
; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 [[START]], [[N_VEC]]
98+
; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], 8
99+
; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]]
100+
; CHECK: [[VEC_EPILOG_PH]]:
101+
; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
102+
; CHECK-NEXT: [[N_MOD_VF2:%.*]] = urem i64 [[START]], 8
103+
; CHECK-NEXT: [[N_VEC3:%.*]] = sub i64 [[START]], [[N_MOD_VF2]]
104+
; CHECK-NEXT: [[IND_END1:%.*]] = sub i64 [[START]], [[N_VEC3]]
105+
; CHECK-NEXT: [[IND_END5:%.*]] = getelementptr i8, ptr [[PTR_START]], i64 [[N_VEC3]]
106+
; CHECK-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]
107+
; CHECK: [[VEC_EPILOG_VECTOR_BODY]]:
108+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT10:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
109+
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
110+
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PTR_START]], i64 [[TMP0]]
111+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i32 0
112+
; CHECK-NEXT: store <8 x i8> zeroinitializer, ptr [[TMP2]], align 1
113+
; CHECK-NEXT: [[INDEX_NEXT10]] = add nuw i64 [[INDEX]], 8
114+
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT10]], [[N_VEC3]]
115+
; CHECK-NEXT: br i1 [[TMP7]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
116+
; CHECK: [[VEC_EPILOG_MIDDLE_BLOCK]]:
117+
; CHECK-NEXT: [[CMP_N11:%.*]] = icmp eq i64 [[START]], [[N_VEC3]]
118+
; CHECK-NEXT: br i1 [[CMP_N11]], label %[[EXIT_LOOPEXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
119+
; CHECK: [[VEC_EPILOG_SCALAR_PH]]:
120+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END1]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END]], %[[VEC_EPILOG_ITER_CHECK]] ], [ [[START]], %[[ITER_CHECK]] ]
121+
; CHECK-NEXT: [[BC_RESUME_VAL7:%.*]] = phi ptr [ [[IND_END5]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END6]], %[[VEC_EPILOG_ITER_CHECK]] ], [ [[PTR_START]], %[[ITER_CHECK]] ]
122+
; CHECK-NEXT: br label %[[LOOP:.*]]
123+
; CHECK: [[LOOP]]:
124+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ]
125+
; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL7]], %[[VEC_EPILOG_SCALAR_PH]] ]
126+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], -1
127+
; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 1
128+
; CHECK-NEXT: store i8 0, ptr [[PTR_IV]], align 1
129+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 0
130+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
131+
; CHECK: [[EXIT_LOOPEXIT]]:
132+
; CHECK-NEXT: br label %[[EXIT]]
133+
; CHECK: [[EXIT]]:
134+
; CHECK-NEXT: ret void
135+
;
136+
entry:
137+
%a.ext = zext i8 %a to i64
138+
%start = call i64 @llvm.umin.i64(i64 %b, i64 %a.ext)
139+
%c = icmp eq i64 %start, 0
140+
br i1 %c, label %exit, label %loop
141+
142+
loop:
143+
%iv = phi i64 [ %start, %entry ], [ %iv.next, %loop ]
144+
%ptr.iv = phi ptr [ %ptr.start, %entry ], [ %ptr.iv.next, %loop ]
145+
%iv.next = add i64 %iv, -1
146+
%ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 1
147+
store i8 0, ptr %ptr.iv, align 1
148+
%ec = icmp eq i64 %iv.next, 0
149+
br i1 %ec, label %exit, label %loop
150+
151+
exit:
152+
ret void
153+
}
154+
155+
define void @test_exit_branch_cost(ptr %dst, i64 %x, i32 %y, ptr %dst.1, i1 %c.4, ptr %src, ptr %dst.3, i1 %c.3, ptr %dst.2) {
156+
; CHECK-LABEL: define void @test_exit_branch_cost(
157+
; CHECK-SAME: ptr [[DST:%.*]], i64 [[X:%.*]], i32 [[Y:%.*]], ptr [[DST_1:%.*]], i1 [[C_4:%.*]], ptr [[SRC:%.*]], ptr [[DST_3:%.*]], i1 [[C_3:%.*]], ptr [[DST_2:%.*]]) {
158+
; CHECK-NEXT: [[ENTRY:.*]]:
159+
; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
160+
; CHECK: [[LOOP_HEADER]]:
161+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
162+
; CHECK-NEXT: [[C1:%.*]] = icmp eq i64 [[X]], 0
163+
; CHECK-NEXT: br i1 [[C1]], label %[[THEN_4:.*]], label %[[THEN_1:.*]]
164+
; CHECK: [[THEN_1]]:
165+
; CHECK-NEXT: [[AND32831:%.*]] = and i32 [[Y]], 1
166+
; CHECK-NEXT: store i64 0, ptr [[DST_1]], align 8
167+
; CHECK-NEXT: [[C_2:%.*]] = icmp eq i32 [[Y]], 0
168+
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C_4]], i1 [[C_3]], i1 false
169+
; CHECK-NEXT: br i1 [[OR_COND]], label %[[THEN_2:.*]], label %[[ELSE_1:.*]]
170+
; CHECK: [[ELSE_1]]:
171+
; CHECK-NEXT: store i64 0, ptr [[DST_3]], align 8
172+
; CHECK-NEXT: br label %[[THEN_2]]
173+
; CHECK: [[THEN_2]]:
174+
; CHECK-NEXT: br i1 [[C_3]], label %[[THEN_3:.*]], label %[[LOOP_LATCH]]
175+
; CHECK: [[THEN_3]]:
176+
; CHECK-NEXT: br i1 [[C_4]], label %[[THEN_5:.*]], label %[[ELSE_2:.*]]
177+
; CHECK: [[THEN_4]]:
178+
; CHECK-NEXT: call void @llvm.assume(i1 [[C_4]])
179+
; CHECK-NEXT: br label %[[THEN_5]]
180+
; CHECK: [[THEN_5]]:
181+
; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 1, %[[THEN_4]] ], [ 0, %[[THEN_3]] ]
182+
; CHECK-NEXT: store i64 [[TMP0]], ptr [[DST_2]], align 8
183+
; CHECK-NEXT: br label %[[ELSE_2]]
184+
; CHECK: [[ELSE_2]]:
185+
; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[SRC]], align 8
186+
; CHECK-NEXT: store i64 [[L]], ptr [[DST]], align 8
187+
; CHECK-NEXT: br label %[[LOOP_LATCH]]
188+
; CHECK: [[LOOP_LATCH]]:
189+
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
190+
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 64
191+
; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
192+
; CHECK: [[EXIT]]:
193+
; CHECK-NEXT: ret void
194+
;
195+
entry:
196+
br label %loop.header
197+
198+
loop.header:
199+
%iv = phi i64 [ %iv.next, %loop.latch ], [ 0, %entry ]
200+
%c1 = icmp eq i64 %x, 0
201+
br i1 %c1, label %then.4, label %then.1
202+
203+
then.1:
204+
%and32831 = and i32 %y, 1
205+
store i64 0, ptr %dst.1, align 8
206+
%c.2 = icmp eq i32 %y, 0
207+
%or.cond = select i1 %c.4, i1 %c.3, i1 false
208+
br i1 %or.cond, label %then.2, label %else.1
209+
210+
else.1: ; preds = %then.1
211+
store i64 0, ptr %dst.3, align 8
212+
br label %then.2
213+
214+
then.2:
215+
br i1 %c.3, label %then.3, label %loop.latch
216+
217+
then.3:
218+
br i1 %c.4, label %then.5, label %else.2
219+
220+
then.4:
221+
call void @llvm.assume(i1 %c.4)
222+
br label %then.5
223+
224+
then.5:
225+
%1 = phi i64 [ 1, %then.4 ], [ 0, %then.3 ]
226+
store i64 %1, ptr %dst.2, align 8
227+
br label %else.2
228+
229+
else.2:
230+
%l = load i64, ptr %src, align 8
231+
store i64 %l, ptr %dst, align 8
232+
br label %loop.latch
233+
234+
loop.latch:
235+
%iv.next = add i64 %iv, 1
236+
%ec = icmp eq i64 %iv, 64
237+
br i1 %ec, label %exit, label %loop.header
238+
239+
exit:
240+
ret void
241+
}
242+
243+
declare void @llvm.assume(i1 noundef)
244+
declare i64 @llvm.umin.i64(i64, i64)
245+
;.
246+
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
247+
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
248+
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
249+
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
250+
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
251+
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}
252+
; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META2]], [[META1]]}
253+
;.

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