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3 files changed

+7
-9
lines changed

3 files changed

+7
-9
lines changed

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3578,11 +3578,10 @@ SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) con
35783578
return SDValue();
35793579
}
35803580

3581-
return LowerF64ToF16(N0, Op.getValueType(), DL, DAG);
3581+
return LowerF64ToF16(N0, DL, DAG);
35823582
}
35833583

3584-
SDValue AMDGPUTargetLowering::LowerF64ToF16(SDValue Src, EVT ResTy,
3585-
const SDLoc &DL,
3584+
SDValue AMDGPUTargetLowering::LowerF64ToF16(SDValue Src, const SDLoc &DL,
35863585
SelectionDAG &DAG) const {
35873586
assert(Src.getSimpleValueType() == MVT::f64);
35883587

@@ -3667,8 +3666,7 @@ SDValue AMDGPUTargetLowering::LowerF64ToF16(SDValue Src, EVT ResTy,
36673666
Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,
36683667
DAG.getConstant(0x8000, DL, MVT::i32));
36693668

3670-
V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
3671-
return DAG.getZExtOrTrunc(V, DL, ResTy);
3669+
return DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);
36723670
}
36733671

36743672
SDValue AMDGPUTargetLowering::LowerFP_TO_INT(const SDValue Op,

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,8 +97,7 @@ class AMDGPUTargetLowering : public TargetLowering {
9797
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
9898
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
9999

100-
SDValue LowerF64ToF16(SDValue Src, EVT ResTy, const SDLoc &DL,
101-
SelectionDAG &DAG) const;
100+
SDValue LowerF64ToF16(SDValue Src, const SDLoc &DL, SelectionDAG &DAG) const;
102101

103102
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
104103

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6905,8 +6905,9 @@ SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
69056905
SDValue Src32 = DAG.getNode(ISD::FP_ROUND, DL, MVT::f32, Src, Flags);
69066906
return DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, Src32, Flags);
69076907
} else {
6908-
SDValue FpToFp16 = LowerF64ToF16(Src, MVT::i16, DL, DAG);
6909-
return DAG.getNode(ISD::BITCAST, DL, MVT::f16, FpToFp16);
6908+
SDValue FpToFp16 = LowerF64ToF16(Src, DL, DAG);
6909+
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
6910+
return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);
69106911
}
69116912
} else {
69126913
SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);

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