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[CallingConv] Return ArrayRef from AllocateRegBlock() (NFC)
Instead of returning the first register, return the ArrayRef containing the whole block. Existing users rely on the fact that the register block only contains adjacently-numbered registers and it's possible to get the remaining registers in the block by just incrementing the register. Returning an ArrayRef allows more generic usage with non-adjacent registers.
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3 files changed

+22
-21
lines changed

3 files changed

+22
-21
lines changed

llvm/include/llvm/CodeGen/CallingConvLower.h

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -357,12 +357,13 @@ class CCState {
357357
return Reg;
358358
}
359359

360-
/// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
361-
/// registers. If this is not possible, return zero. Otherwise, return the first
362-
/// register of the block that were allocated, marking the entire block as allocated.
363-
MCPhysReg AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
360+
/// Attempt to allocate a block of RegsRequired consecutive registers.
361+
/// If this is not possible, return an empty range. Otherwise, return a
362+
/// range of consecutive registers, marking the entire block as allocated.
363+
ArrayRef<MCPhysReg> AllocateRegBlock(ArrayRef<MCPhysReg> Regs,
364+
unsigned RegsRequired) {
364365
if (RegsRequired > Regs.size())
365-
return 0;
366+
return {};
366367

367368
for (unsigned StartIdx = 0; StartIdx <= Regs.size() - RegsRequired;
368369
++StartIdx) {
@@ -379,11 +380,11 @@ class CCState {
379380
for (unsigned BlockIdx = 0; BlockIdx < RegsRequired; ++BlockIdx) {
380381
MarkAllocated(Regs[StartIdx + BlockIdx]);
381382
}
382-
return Regs[StartIdx];
383+
return Regs.slice(StartIdx, RegsRequired);
383384
}
384385
}
385386
// No block was available
386-
return 0;
387+
return {};
387388
}
388389

389390
/// Version of AllocateReg with list of registers to be shadowed.

llvm/lib/Target/AArch64/AArch64CallingConvention.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -176,27 +176,27 @@ static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
176176
// [N x i32] arguments get packed into x-registers on Darwin's arm64_32
177177
// because that's how the armv7k Clang front-end emits small structs.
178178
unsigned EltsPerReg = (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32) ? 2 : 1;
179-
unsigned RegResult = State.AllocateRegBlock(
179+
ArrayRef<MCPhysReg> RegResult = State.AllocateRegBlock(
180180
RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg);
181-
if (RegResult && EltsPerReg == 1) {
182-
for (auto &It : PendingMembers) {
183-
It.convertToReg(RegResult);
181+
if (!RegResult.empty() && EltsPerReg == 1) {
182+
for (const auto &[It, Reg] : zip(PendingMembers, RegResult)) {
183+
It.convertToReg(Reg);
184184
State.addLoc(It);
185-
++RegResult;
186185
}
187186
PendingMembers.clear();
188187
return true;
189-
} else if (RegResult) {
188+
} else if (!RegResult.empty()) {
190189
assert(EltsPerReg == 2 && "unexpected ABI");
191190
bool UseHigh = false;
192191
CCValAssign::LocInfo Info;
192+
unsigned RegIdx = 0;
193193
for (auto &It : PendingMembers) {
194194
Info = UseHigh ? CCValAssign::AExtUpper : CCValAssign::ZExt;
195-
State.addLoc(CCValAssign::getReg(It.getValNo(), MVT::i32, RegResult,
196-
MVT::i64, Info));
195+
State.addLoc(CCValAssign::getReg(It.getValNo(), MVT::i32,
196+
RegResult[RegIdx], MVT::i64, Info));
197197
UseHigh = !UseHigh;
198198
if (!UseHigh)
199-
++RegResult;
199+
++RegIdx;
200200
}
201201
PendingMembers.clear();
202202
return true;

llvm/lib/Target/ARM/ARMCallingConv.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -228,12 +228,12 @@ static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned ValNo, MVT ValVT,
228228
break;
229229
}
230230

231-
unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size());
232-
if (RegResult) {
233-
for (CCValAssign &PendingMember : PendingMembers) {
234-
PendingMember.convertToReg(RegResult);
231+
ArrayRef<MCPhysReg> RegResult =
232+
State.AllocateRegBlock(RegList, PendingMembers.size());
233+
if (!RegResult.empty()) {
234+
for (const auto &[PendingMember, Reg] : zip(PendingMembers, RegResult)) {
235+
PendingMember.convertToReg(Reg);
235236
State.addLoc(PendingMember);
236-
++RegResult;
237237
}
238238
PendingMembers.clear();
239239
return true;

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