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KanRobertKanRobert
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[X86][NFC] Move classe BinOp*, UnaryOp* to X86InstrUtils.td and simplify CRC32 definitions
1. BinOp*, UnaryOp* will be used in X86InstrShiftRotate.td for the APX support 2. Simplify CRC32 definitions to extract the NFC change in 76434 into a separate commit
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‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 0 additions & 369 deletions
Original file line numberDiff line numberDiff line change
@@ -44,375 +44,6 @@ def PLEA32r : PseudoI<(outs GR32:$dst), (ins anymem:$src), []>;
4444
def PLEA64r : PseudoI<(outs GR64:$dst), (ins anymem:$src), []>;
4545
}
4646

47-
// BinOpRR - Instructions that read "reg, reg".
48-
class BinOpRR<bits<8> o, string m, string args, X86TypeInfo t, dag out, list<dag> p>
49-
: ITy<o, MRMDestReg, t, out, (ins t.RegClass:$src1, t.RegClass:$src2), m,
50-
args, p>, Sched<[WriteALU]>;
51-
// BinOpRR_F - Instructions that read "reg, reg" and write EFLAGS only.
52-
class BinOpRR_F<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
53-
: BinOpRR<o, m, binop_args, t, (outs),
54-
[(set EFLAGS, (node t.RegClass:$src1, t.RegClass:$src2))]>,
55-
DefEFLAGS;
56-
// BinOpRR_F_Rev - Reversed encoding of BinOpRR_F
57-
class BinOpRR_F_Rev<bits<8> o, string m, X86TypeInfo t>
58-
: BinOpRR_F<o, m, t, null_frag>, DisassembleOnly {
59-
let Form = MRMSrcReg;
60-
}
61-
// BinOpRR_R - Instructions that read "reg, reg" and write "reg".
62-
class BinOpRR_R<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
63-
: BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t,
64-
(outs t.RegClass:$dst), []>, NDD<ndd>;
65-
// BinOpRR_R_Rev - Reversed encoding of BinOpRR_R
66-
class BinOpRR_R_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
67-
: BinOpRR_R<o, m, t, ndd>, DisassembleOnly {
68-
let Form = MRMSrcReg;
69-
}
70-
// BinOpRR_RF - Instructions that read "reg, reg", and write "reg", EFLAGS.
71-
class BinOpRR_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit ndd = 0>
72-
: BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t,
73-
(outs t.RegClass:$dst),
74-
[(set t.RegClass:$dst, EFLAGS,
75-
(node t.RegClass:$src1, t.RegClass:$src2))]>, DefEFLAGS, NDD<ndd>;
76-
// BinOpRR_RF_Rev - Reversed encoding of BinOpRR_RF.
77-
class BinOpRR_RF_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
78-
: BinOpRR_RF<o, m, t, null_frag, ndd>, DisassembleOnly {
79-
let Form = MRMSrcReg;
80-
}
81-
// BinOpRRF_RF - Instructions that read "reg, reg", write "reg" and read/write
82-
// EFLAGS.
83-
class BinOpRRF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit ndd = 0>
84-
: BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
85-
[(set t.RegClass:$dst, EFLAGS,
86-
(node t.RegClass:$src1, t.RegClass:$src2,
87-
EFLAGS))]>, DefEFLAGS, UseEFLAGS, NDD<ndd> {
88-
let SchedRW = [WriteADC];
89-
}
90-
// BinOpRRF_RF_Rev - Reversed encoding of BinOpRRF_RF
91-
class BinOpRRF_RF_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
92-
: BinOpRRF_RF<o, m, t, null_frag, ndd>, DisassembleOnly {
93-
let Form = MRMSrcReg;
94-
}
95-
96-
// BinOpRM - Instructions that read "reg, [mem]".
97-
class BinOpRM<bits<8> o, string m, string args, X86TypeInfo t, dag out, list<dag> p>
98-
: ITy<o, MRMSrcMem, t, out, (ins t.RegClass:$src1, t.MemOperand:$src2), m,
99-
args, p>,
100-
Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]> {
101-
let mayLoad = 1;
102-
}
103-
// BinOpRM_F - Instructions that read "reg, [mem]" and write EFLAGS only.
104-
class BinOpRM_F<bits<8> o, string m, X86TypeInfo t, SDNode node>
105-
: BinOpRM<o, m, binop_args, t, (outs),
106-
[(set EFLAGS, (node t.RegClass:$src1,
107-
(t.LoadNode addr:$src2)))]>, DefEFLAGS;
108-
// BinOpRM_R - Instructions that read "reg, [mem]", and write "reg".
109-
class BinOpRM_R<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
110-
: BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
111-
[]>, NDD<ndd>;
112-
// BinOpRM_RF - Instructions that read "reg, [mem]", and write "reg", EFLAGS.
113-
class BinOpRM_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit ndd = 0>
114-
: BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
115-
[(set t.RegClass:$dst, EFLAGS, (node t.RegClass:$src1,
116-
(t.LoadNode addr:$src2)))]>, DefEFLAGS, NDD<ndd>;
117-
// BinOpRMF_RF - Instructions that read "reg, [mem]", write "reg" and read/write
118-
// EFLAGS.
119-
class BinOpRMF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit ndd = 0>
120-
: BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
121-
[(set t.RegClass:$dst, EFLAGS,
122-
(node t.RegClass:$src1, (t.LoadNode addr:$src2), EFLAGS))]>,
123-
DefEFLAGS, UseEFLAGS, NDD<ndd> {
124-
let SchedRW = [WriteADC.Folded, WriteADC.ReadAfterFold,
125-
// base, scale, index, offset, segment.
126-
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
127-
// implicit register read.
128-
WriteADC.ReadAfterFold];
129-
}
130-
131-
// BinOpRI - Instructions that read "reg, imm".
132-
class BinOpRI<bits<8> o, string m, string args, X86TypeInfo t, Format f, dag out, list<dag> p>
133-
: ITy<o, f, t, out, (ins t.RegClass:$src1, t.ImmOperand:$src2), m,
134-
args, p>, Sched<[WriteALU]> {
135-
let ImmT = t.ImmEncoding;
136-
}
137-
// BinOpRI_F - Instructions that read "reg, imm" and write EFLAGS only.
138-
class BinOpRI_F<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node,
139-
Format f>
140-
: BinOpRI<o, m, binop_args, t, f, (outs),
141-
[(set EFLAGS, (node t.RegClass:$src1,
142-
t.ImmOperator:$src2))]>, DefEFLAGS;
143-
// BinOpRI_R - Instructions that read "reg, imm" and write "reg".
144-
class BinOpRI_R<bits<8> o, string m, X86TypeInfo t, Format f, bit ndd = 0>
145-
: BinOpRI<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst),
146-
[]>, NDD<ndd>;
147-
// BinOpRI_RF - Instructions that read "reg, imm" and write "reg", EFLAGS.
148-
class BinOpRI_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, Format f, bit ndd = 0>
149-
: BinOpRI<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst),
150-
[(set t.RegClass:$dst, EFLAGS,
151-
(node t.RegClass:$src1, t.ImmOperator:$src2))]>, DefEFLAGS, NDD<ndd>;
152-
// BinOpRIF_RF - Instructions that read "reg, imm", write "reg" and read/write
153-
// EFLAGS.
154-
class BinOpRIF_RF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f, bit ndd = 0>
155-
: BinOpRI<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst),
156-
[(set t.RegClass:$dst, EFLAGS,
157-
(node t.RegClass:$src1, t.ImmOperator:$src2,
158-
EFLAGS))]>, DefEFLAGS, UseEFLAGS, NDD<ndd> {
159-
let SchedRW = [WriteADC];
160-
}
161-
// BinOpRI8 - Instructions that read "reg, imm8".
162-
class BinOpRI8<bits<8> o, string m, string args, X86TypeInfo t, Format f, dag out>
163-
: ITy<o, f, t, out, (ins t.RegClass:$src1, t.Imm8Operand:$src2), m,
164-
args, []>, Sched<[WriteALU]> {
165-
let ImmT = Imm8;
166-
}
167-
// BinOpRI8_F - Instructions that read "reg, imm8" and write EFLAGS only.
168-
class BinOpRI8_F<bits<8> o, string m, X86TypeInfo t, Format f>
169-
: BinOpRI8<o, m, binop_args, t, f, (outs)>, DefEFLAGS;
170-
// BinOpRI8_R - Instructions that read "reg, imm8" and write "reg".
171-
class BinOpRI8_R<bits<8> o, string m, X86TypeInfo t, Format f, bit ndd = 0>
172-
: BinOpRI8<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst)>, NDD<ndd>;
173-
// BinOpRI8_RF - Instructions that read "reg, imm8" and write "reg", EFLAGS.
174-
class BinOpRI8_RF<bits<8> o, string m, X86TypeInfo t, Format f, bit ndd = 0>
175-
: BinOpRI8<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst)>, DefEFLAGS, NDD<ndd>;
176-
// BinOpRI8F_RF - Instructions that read "reg, imm", write "reg" and read/write
177-
// EFLAGS.
178-
class BinOpRI8F_RF<bits<8> o, string m, X86TypeInfo t, Format f, bit ndd = 0>
179-
: BinOpRI8<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, f, (outs t.RegClass:$dst)>, DefEFLAGS, UseEFLAGS, NDD<ndd> {
180-
let SchedRW = [WriteADC];
181-
}
182-
183-
// BinOpMR - Instructions that read "[mem], reg".
184-
class BinOpMR<bits<8> o, string m, string args, X86TypeInfo t, dag out, list<dag> p>
185-
: ITy<o, MRMDestMem, t, out, (ins t.MemOperand:$src1, t.RegClass:$src2), m,
186-
args, p> {
187-
let mayLoad = 1;
188-
let SchedRW = [WriteALU.Folded, WriteALU.ReadAfterFold];
189-
}
190-
// BinOpMR_R - Instructions that read "[mem], reg", and write "reg".
191-
class BinOpMR_R<bits<8> o, string m, X86TypeInfo t>
192-
: BinOpMR<o, m, binop_ndd_args, t, (outs t.RegClass:$dst), []>, NDD<1>;
193-
// BinOpMR_RF - Instructions that read "[mem], reg", and write "reg", EFLAGS.
194-
class BinOpMR_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
195-
: BinOpMR<o, m, binop_ndd_args, t, (outs t.RegClass:$dst),
196-
[(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1),
197-
t.RegClass:$src2))]>, DefEFLAGS, NDD<1>;
198-
// BinOpMR_F - Instructions that read "[mem], imm8" and write EFLAGS only.
199-
class BinOpMR_F<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
200-
: BinOpMR<o, m, binop_args, t, (outs),
201-
[(set EFLAGS, (node (t.LoadNode addr:$src1), t.RegClass:$src2))]>,
202-
Sched<[WriteALU.Folded, ReadDefault, ReadDefault, ReadDefault,
203-
ReadDefault, ReadDefault, WriteALU.ReadAfterFold]>, DefEFLAGS;
204-
// BinOpMR_M - Instructions that read "[mem], reg" and write "[mem]".
205-
class BinOpMR_M<bits<8> o, string m, X86TypeInfo t>
206-
: BinOpMR<o, m, binop_args, t, (outs), []>,
207-
Sched<[WriteALURMW,
208-
// base, scale, index, offset, segment
209-
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault]> {
210-
let mayStore = 1;
211-
}
212-
// BinOpMR_MF - Instructions that read "[mem], reg" and write "[mem]", EFLAGS.
213-
class BinOpMR_MF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
214-
: BinOpMR<o, m, binop_args, t, (outs),
215-
[(store (node (load addr:$src1), t.RegClass:$src2), addr:$src1),
216-
(implicit EFLAGS)]>,
217-
Sched<[WriteALURMW,
218-
// base, scale, index, offset, segment
219-
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
220-
WriteALU.ReadAfterFold]>, // reg
221-
DefEFLAGS {
222-
let mayStore = 1;
223-
}
224-
// BinOpMRF_RF - Instructions that read "[mem], reg", write "reg" and
225-
// read/write EFLAGS.
226-
class BinOpMRF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
227-
: BinOpMR<o, m, binop_ndd_args, t, (outs t.RegClass:$dst),
228-
[(set t.RegClass:$dst, EFLAGS, (node (load addr:$src1),
229-
t.RegClass:$src2, EFLAGS))]>, DefEFLAGS, UseEFLAGS, NDD<1>,
230-
Sched<[WriteADC.Folded, WriteADC.ReadAfterFold]>;
231-
// BinOpMRF_MF - Instructions that read "[mem], reg", write "[mem]" and
232-
// read/write EFLAGS.
233-
class BinOpMRF_MF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
234-
: BinOpMR<o, m, binop_args, t, (outs),
235-
[(store (node (load addr:$src1), t.RegClass:$src2, EFLAGS),
236-
addr:$src1), (implicit EFLAGS)]>,
237-
Sched<[WriteADCRMW,
238-
// base, scale, index, offset, segment
239-
ReadDefault, ReadDefault, ReadDefault,
240-
ReadDefault, ReadDefault,
241-
WriteALU.ReadAfterFold, // reg
242-
WriteALU.ReadAfterFold]>, // EFLAGS
243-
DefEFLAGS, UseEFLAGS {
244-
let mayStore = 1;
245-
}
246-
247-
// BinOpMI - Instructions that read "[mem], imm".
248-
class BinOpMI<bits<8> o, string m, string args, X86TypeInfo t, Format f, dag out, list<dag> p>
249-
: ITy<o, f, t, out, (ins t.MemOperand:$src1, t.ImmOperand:$src2), m,
250-
args, p> {
251-
let ImmT = t.ImmEncoding;
252-
let mayLoad = 1;
253-
}
254-
// BinOpMI_F - Instructions that read "[mem], imm" and write EFLAGS only.
255-
class BinOpMI_F<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node,
256-
Format f>
257-
: BinOpMI<o, m, binop_args, t, f, (outs),
258-
[(set EFLAGS, (node (t.LoadNode addr:$src1), t.ImmOperator:$src2))]>,
259-
Sched<[WriteALU.Folded]>, DefEFLAGS;
260-
// BinOpMI_R - Instructions that read "[mem], imm" and write "reg".
261-
class BinOpMI_R<bits<8> o, string m, X86TypeInfo t, Format f>
262-
: BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst), []>,
263-
Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>;
264-
// BinOpMI_R - Instructions that read "[mem], imm" and write "reg", EFLAGS.
265-
class BinOpMI_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node,
266-
Format f>
267-
: BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst),
268-
[(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1), t.ImmOperator:$src2))]>,
269-
Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>;
270-
// BinOpMI_M - Instructions that read "[mem], imm" and write "[mem]".
271-
class BinOpMI_M<bits<8> o, string m, X86TypeInfo t, Format f>
272-
: BinOpMI<o, m, binop_args, t, f, (outs), []>, Sched<[WriteALURMW]> {
273-
let mayStore = 1;
274-
}
275-
// BinOpMI_MF - Instructions that read "[mem], imm" and write "[mem]", EFLAGS.
276-
class BinOpMI_MF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, Format f>
277-
: BinOpMI<o, m, binop_args, t, f, (outs),
278-
[(store (node (t.VT (load addr:$src1)),
279-
t.ImmOperator:$src2), addr:$src1), (implicit EFLAGS)]>,
280-
Sched<[WriteALURMW]>, DefEFLAGS {
281-
let mayStore = 1;
282-
}
283-
// BinOpMIF_RF - Instructions that read "[mem], imm", write "reg" and
284-
// read/write EFLAGS.
285-
class BinOpMIF_RF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f>
286-
: BinOpMI<o, m, binop_ndd_args, t, f, (outs t.RegClass:$dst),
287-
[(set t.RegClass:$dst, EFLAGS, (node (t.VT (load addr:$src1)),
288-
t.ImmOperator:$src2, EFLAGS))]>,
289-
Sched<[WriteADC.Folded, WriteADC.ReadAfterFold]>, DefEFLAGS, UseEFLAGS, NDD<1>;
290-
// BinOpMIF_MF - Instructions that read "[mem], imm", write "[mem]" and
291-
// read/write EFLAGS.
292-
class BinOpMIF_MF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f>
293-
: BinOpMI<o, m, binop_args, t, f, (outs),
294-
[(store (node (t.VT (load addr:$src1)),
295-
t.ImmOperator:$src2, EFLAGS), addr:$src1), (implicit EFLAGS)]>,
296-
Sched<[WriteADCRMW]>, DefEFLAGS, UseEFLAGS {
297-
let mayStore = 1;
298-
}
299-
300-
// BinOpMI8 - Instructions that read "[mem], imm8".
301-
class BinOpMI8<string m, string args, X86TypeInfo t, Format f, dag out>
302-
: ITy<0x83, f, t, out, (ins t.MemOperand:$src1, t.Imm8Operand:$src2), m,
303-
args, []> {
304-
let ImmT = Imm8;
305-
let mayLoad = 1;
306-
}
307-
// BinOpMI8_F - Instructions that read "[mem], imm8" and write EFLAGS only.
308-
class BinOpMI8_F<string m, X86TypeInfo t, Format f>
309-
: BinOpMI8<m, binop_args, t, f, (outs)>, Sched<[WriteALU.Folded]>, DefEFLAGS;
310-
// BinOpMI8_R - Instructions that read "[mem], imm8" and write "reg".
311-
class BinOpMI8_R<string m, X86TypeInfo t, Format f>
312-
: BinOpMI8<m, binop_ndd_args, t, f, (outs t.RegClass:$dst)>, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>;
313-
// BinOpMI8_RF - Instructions that read "[mem], imm8" and write "reg"/EFLAGS.
314-
class BinOpMI8_RF<string m, X86TypeInfo t, Format f>
315-
: BinOpMI8<m, binop_ndd_args, t, f, (outs t.RegClass:$dst)>, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>;
316-
// BinOpMI8_M - Instructions that read "[mem], imm8" and write "[mem]".
317-
class BinOpMI8_M<string m, X86TypeInfo t, Format f>
318-
: BinOpMI8<m, binop_args, t, f, (outs)>, Sched<[WriteALURMW]> {
319-
let mayStore = 1;
320-
}
321-
// BinOpMI8_MF - Instructions that read "[mem], imm8" and write "[mem]", EFLAGS.
322-
class BinOpMI8_MF<string m, X86TypeInfo t, Format f>
323-
: BinOpMI8<m, binop_args, t, f, (outs)>, Sched<[WriteALURMW]>, DefEFLAGS {
324-
let mayStore = 1;
325-
}
326-
// BinOpMI8F_RF - Instructions that read "[mem], imm8", write "reg" and
327-
// read/write EFLAGS.
328-
class BinOpMI8F_RF<string m, X86TypeInfo t, Format f>
329-
: BinOpMI8<m, binop_ndd_args, t, f, (outs t.RegClass:$dst)>,
330-
Sched<[WriteADC.Folded, WriteADC.ReadAfterFold]>, DefEFLAGS, UseEFLAGS, NDD<1>;
331-
// BinOpMI8F_MF - Instructions that read "[mem], imm8", write "[mem]" and
332-
// read/write EFLAGS.
333-
class BinOpMI8F_MF<string m, X86TypeInfo t, Format f>
334-
: BinOpMI8<m, binop_args, t, f, (outs)>, Sched<[WriteADCRMW]>, DefEFLAGS, UseEFLAGS {
335-
let mayStore = 1;
336-
}
337-
338-
// BinOpAI - Instructions that read "a-reg imm" (Accumulator register).
339-
class BinOpAI<bits<8> o, string m, X86TypeInfo t, Register areg, string args>
340-
: ITy<o, RawFrm, t, (outs), (ins t.ImmOperand:$src), m, args, []>,
341-
Sched<[WriteALU]> {
342-
let ImmT = t.ImmEncoding;
343-
let Uses = [areg];
344-
}
345-
// BinOpAI_F - Instructions that read "a-reg imm" and write EFLAGS only.
346-
class BinOpAI_F<bits<8> o, string m, X86TypeInfo t, Register areg, string args>
347-
: BinOpAI<o, m, t, areg, args>, DefEFLAGS;
348-
349-
// BinOpAI_AF - Instructions that read "a-reg imm" and write a-reg/EFLAGS.
350-
class BinOpAI_AF<bits<8> o, string m, X86TypeInfo t, Register areg,
351-
string args> : BinOpAI<o, m, t, areg, args> {
352-
let Defs = [areg, EFLAGS];
353-
}
354-
// BinOpAIF_AF - Instructions that read "a-reg imm", write a-reg and read/write
355-
// EFLAGS.
356-
class BinOpAIF_AF<bits<8> o, string m, X86TypeInfo t, Register areg,
357-
string args> : BinOpAI<o, m, t, areg, args> {
358-
let Uses = [areg, EFLAGS];
359-
let Defs = [areg, EFLAGS];
360-
let SchedRW = [WriteADC];
361-
}
362-
363-
// UnaryOpR - Instructions that read "reg".
364-
class UnaryOpR<bits<8> o, Format f, string m, string args, X86TypeInfo t,
365-
dag out, list<dag> p>
366-
: ITy<o, f, t, out, (ins t.RegClass:$src1), m, args, p>, Sched<[WriteALU]>;
367-
// UnaryOpR_R - Instructions that read "reg" and write "reg".
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class UnaryOpR_R<bits<8> o, Format f, string m, X86TypeInfo t,
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SDPatternOperator node, bit ndd = 0>
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: UnaryOpR<o, f, m, !if(!eq(ndd, 0), unaryop_args, unaryop_ndd_args), t,
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(outs t.RegClass:$dst),
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[(set t.RegClass:$dst, (node t.RegClass:$src1))]>, NDD<ndd>;
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// UnaryOpR_RF - Instructions that read "reg" and write "reg"/EFLAGS.
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class UnaryOpR_RF<bits<8> o, Format f, string m, X86TypeInfo t,
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SDPatternOperator node, bit ndd = 0>
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: UnaryOpR<o, f, m, !if(!eq(ndd, 0), unaryop_args, unaryop_ndd_args), t,
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(outs t.RegClass:$dst),
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[(set t.RegClass:$dst, (node t.RegClass:$src1)),
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(implicit EFLAGS)]>, DefEFLAGS, NDD<ndd>;
380-
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// UnaryOpM - Instructions that read "[mem]".
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class UnaryOpM<bits<8> o, Format f, string m, string args, X86TypeInfo t,
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dag out, list<dag> p>
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: ITy<o, f, t, out, (ins t.MemOperand:$src1), m, args, p> {
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let mayLoad = 1;
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}
387-
// UnaryOpM_R - Instructions that read "[mem]" and writes "reg".
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class UnaryOpM_R<bits<8> o, Format f, string m, X86TypeInfo t,
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SDPatternOperator node>
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: UnaryOpM<o, f, m, unaryop_ndd_args, t, (outs t.RegClass:$dst),
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[(set t.RegClass:$dst, (node (t.LoadNode addr:$src1)))]>,
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Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>;
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// UnaryOpM_RF - Instructions that read "[mem]" and writes "reg"/EFLAGS.
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class UnaryOpM_RF<bits<8> o, Format f, string m, X86TypeInfo t,
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SDPatternOperator node>
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: UnaryOpM<o, f, m, unaryop_ndd_args, t, (outs t.RegClass:$dst),
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[(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1)))]>,
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Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>;
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// UnaryOpM_M - Instructions that read "[mem]" and writes "[mem]".
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class UnaryOpM_M<bits<8> o, Format f, string m, X86TypeInfo t,
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SDPatternOperator node>
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: UnaryOpM<o, f, m, unaryop_args, t, (outs),
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[(store (node (t.LoadNode addr:$src1)), addr:$src1)]>,
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Sched<[WriteALURMW]>{
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let mayStore = 1;
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}
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// UnaryOpM_MF - Instructions that read "[mem]" and writes "[mem]"/EFLAGS.
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class UnaryOpM_MF<bits<8> o, Format f, string m, X86TypeInfo t,
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SDPatternOperator node>
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: UnaryOpM<o, f, m, unaryop_args, t, (outs),
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[(store (node (t.LoadNode addr:$src1)), addr:$src1),
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(implicit EFLAGS)]>, Sched<[WriteALURMW]>, DefEFLAGS {
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let mayStore = 1;
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}
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41647
//===----------------------------------------------------------------------===//
41748
// MUL/IMUL and DIV/IDIV Instructions
41849
//

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