@@ -703,108 +703,43 @@ def test_riscv64_regs_gpr_fpr(self):
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self .assertTrue (target , VALID_TARGET )
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process = target .LoadCore ("linux-riscv64.gpr_fpr.core" )
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- values = {}
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- alias = {}
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- values ["pc" ] = "0x000000000001016e"
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-
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- values ["ra" ] = "0x00000000000101a4"
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- alias ["x1" ] = "ra"
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-
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- values ["sp" ] = "0x0000003fffc1d2d0"
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- alias ["x2" ] = "sp"
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-
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- values ["gp" ] = "0x0000002ae6eccf50"
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- alias ["x3" ] = "gp"
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-
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- values ["tp" ] = "0x0000003ff3cb5400"
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- alias ["x4" ] = "tp"
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-
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- values ["t0" ] = "0x7f7f7f7fffffffff"
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- alias ["x5" ] = "t0"
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-
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- values ["t1" ] = "0x0000002ae6eb9b1c"
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- alias ["x6" ] = "t1"
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-
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- values ["t2" ] = "0xffffffffffffffff"
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- alias ["x7" ] = "t2"
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-
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- values ["fp" ] = "0x0000003fffc1d300"
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- alias ["x8" ] = "fp"
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-
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- values ["s1" ] = "0x0000002ae6eced98"
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- alias ["x9" ] = "s1"
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-
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- values ["a0" ] = "0x0"
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- alias ["x10" ] = "a0"
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-
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- values ["a1" ] = "0x0000000000010144"
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- alias ["x11" ] = "a1"
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-
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- values ["a2" ] = "0x0000002ae6ecedb0"
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- alias ["x12" ] = "a2"
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-
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- values ["a3" ] = "0xafdbdbff81cf7f81"
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- alias ["x13" ] = "a3"
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-
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- values ["a4" ] = "0x00000000000101e4"
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- alias ["x14" ] = "a4"
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-
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- values ["a5" ] = "0x0"
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- alias ["x15" ] = "a5"
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-
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- values ["a6" ] = "0x2f5b5a40014e0001"
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- alias ["x16" ] = "a6"
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-
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- values ["a7" ] = "0x00000000000000dd"
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- alias ["x17" ] = "a7"
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-
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- values ["s2" ] = "0x0000002ae6ec8860"
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- alias ["x18" ] = "s2"
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-
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- values ["s3" ] = "0x0000002ae6ecedb0"
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- alias ["x19" ] = "s3"
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-
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- values ["s4" ] = "0x0000003fff886c18"
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- alias ["x20" ] = "s4"
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-
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- values ["s5" ] = "0x0000002ae6eceb78"
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- alias ["x21" ] = "s5"
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-
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- values ["s6" ] = "0x0000002ae6ec8860"
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- alias ["x22" ] = "s6"
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-
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- values ["s7" ] = "0x0000002ae6ec8860"
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- alias ["x23" ] = "s7"
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-
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- values ["s8" ] = "0x0"
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- alias ["x24" ] = "s8"
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-
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- values ["s9" ] = "0x000000000000000f"
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- alias ["x25" ] = "s9"
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-
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- values ["s10" ] = "0x0000002ae6ecc8d0"
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- alias ["x26" ] = "s10"
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-
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- values ["s11" ] = "0x0000000000000008"
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- alias ["x27" ] = "s11"
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-
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- values ["t3" ] = "0x0000003ff3be3728"
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- alias ["x28" ] = "t3"
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-
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- values ["t4" ] = "0x0"
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- alias ["x29" ] = "t4"
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-
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- values ["t5" ] = "0x0000000000000002"
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- alias ["x30" ] = "t5"
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-
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- values ["t6" ] = "0x0000002ae6ed08b9"
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- alias ["x31" ] = "t6"
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-
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- values ["zero" ] = "0x0"
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- alias ["x0" ] = "zero"
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-
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- values ["fa5" ] = "0xffffffff423c0000"
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- values ["fcsr" ] = "0x00000000"
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+ values = {
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+ "pc" : ( "0x000000000001016e" , None ),
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+ "zero" : ( "0x0" , "x0" ),
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+ "ra" : ( "0x00000000000101a4" , "x1" ),
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+ "sp" : ( "0x0000003fffc1d2d0" , "x2" ),
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+ "gp" : ( "0x0000002ae6eccf50" , "x3" ),
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+ "tp" : ( "0x0000003ff3cb5400" , "x4" ),
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+ "t0" : ( "0x7f7f7f7fffffffff" , "x5" ),
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+ "t1" : ( "0x0000002ae6eb9b1c" , "x6" ),
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+ "t2" : ( "0xffffffffffffffff" , "x7" ),
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+ "fp" : ( "0x0000003fffc1d300" , "x8" ),
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+ "s1" : ( "0x0000002ae6eced98" , "x9" ),
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+ "a0" : ( "0x0000000000000000" , "x10" ),
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+ "a1" : ( "0x0000000000010144" , "x11" ),
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+ "a2" : ( "0x0000002ae6ecedb0" , "x12" ),
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+ "a3" : ( "0xafdbdbff81cf7f81" , "x13" ),
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+ "a4" : ( "0x00000000000101e4" , "x14" ),
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+ "a5" : ( "0x0000000000000000" , "x15" ),
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+ "a6" : ( "0x2f5b5a40014e0001" , "x16" ),
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+ "a7" : ( "0x00000000000000dd" , "x17" ),
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+ "s2" : ( "0x0000002ae6ec8860" , "x18" ),
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+ "s3" : ( "0x0000002ae6ecedb0" , "x19" ),
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+ "s4" : ( "0x0000003fff886c18" , "x20" ),
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+ "s5" : ( "0x0000002ae6eceb78" , "x21" ),
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+ "s6" : ( "0x0000002ae6ec8860" , "x22" ),
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+ "s7" : ( "0x0000002ae6ec8860" , "x23" ),
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+ "s8" : ( "0x0000000000000000" , "x24" ),
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+ "s9" : ( "0x000000000000000f" , "x25" ),
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+ "s10" : ( "0x0000002ae6ecc8d0" , "x26" ),
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+ "s11" : ( "0x0000000000000008" , "x27" ),
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+ "t3" : ( "0x0000003ff3be3728" , "x28" ),
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+ "t4" : ( "0x0000000000000000" , "x29" ),
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+ "t5" : ( "0x0000000000000002" , "x30" ),
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+ "t6" : ( "0x0000002ae6ed08b9" , "x31" ),
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+ "fa5" : ( "0xffffffff423c0000" , None ),
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+ "fcsr" : ( "0x00000000" , None )
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+ }
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fpr_names = {
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"ft0" ,
@@ -842,25 +777,24 @@ def test_riscv64_regs_gpr_fpr(self):
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}
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fpr_value = "0x0000000000000000"
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- for regname , value in values .items ():
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+ for regname in values :
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+ value , alias = values [regname ]
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self .expect (
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"register read {}" .format (regname ),
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substrs = ["{} = {}" .format (regname , value )],
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)
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+ if alias :
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+ self .expect (
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+ "register read {}" .format (alias ),
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+ substrs = ["{} = {}" .format (regname , value )],
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+ )
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for regname in fpr_names :
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self .expect (
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"register read {}" .format (regname ),
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substrs = ["{} = {}" .format (regname , fpr_value )],
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)
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- for aliasname , regname in alias .items ():
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- value = values [regname ]
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- self .expect (
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- "register read {}" .format (aliasname ),
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- substrs = ["{} = {}" .format (regname , value )],
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- )
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-
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self .expect ("register read --all" )
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@skipIfLLVMTargetMissing ("RISCV" )
@@ -870,118 +804,53 @@ def test_riscv64_regs_gpr_only(self):
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self .assertTrue (target , VALID_TARGET )
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process = target .LoadCore ("linux-riscv64.gpr_only.core" )
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- values = {}
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- alias = {}
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- values ["pc" ] = "0x0000000000010164"
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-
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- values ["ra" ] = "0x0000000000010194"
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- alias ["x1" ] = "ra"
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-
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- values ["sp" ] = "0x00fffffff4d5fcc0"
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- alias ["x2" ] = "sp"
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-
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- values ["gp" ] = "0x0000000000157678"
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- alias ["x3" ] = "gp"
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-
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- values ["tp" ] = "0x00ffffff99c43400"
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- alias ["x4" ] = "tp"
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-
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- values ["t0" ] = "0x00ffffff99c6b260"
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- alias ["x5" ] = "t0"
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-
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- values ["t1" ] = "0x00ffffff99b7bd54"
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- alias ["x6" ] = "t1"
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-
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- values ["t2" ] = "0x0000000003f0b27f"
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- alias ["x7" ] = "t2"
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-
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- values ["fp" ] = "0x00fffffff4d5fcf0"
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- alias ["x8" ] = "fp"
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-
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- values ["s1" ] = "0x0000000000000003"
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- alias ["x9" ] = "s1"
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-
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- values ["a0" ] = "0x0"
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- alias ["x10" ] = "a0"
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-
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- values ["a1" ] = "0x0000000000010144"
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- alias ["x11" ] = "a1"
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-
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- values ["a2" ] = "0x0000000000176460"
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- alias ["x12" ] = "a2"
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-
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- values ["a3" ] = "0x000000000015ee38"
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- alias ["x13" ] = "a3"
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-
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- values ["a4" ] = "0x00000000423c0000"
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- alias ["x14" ] = "a4"
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-
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- values ["a5" ] = "0x0"
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- alias ["x15" ] = "a5"
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-
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- values ["a6" ] = "0x0"
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- alias ["x16" ] = "a6"
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-
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- values ["a7" ] = "0x00000000000000dd"
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- alias ["x17" ] = "a7"
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-
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- values ["s2" ] = "0x0"
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- alias ["x18" ] = "s2"
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-
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- values ["s3" ] = "0x000000000014ddf8"
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- alias ["x19" ] = "s3"
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-
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- values ["s4" ] = "0x000000000003651c"
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- alias ["x20" ] = "s4"
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-
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- values ["s5" ] = "0x00fffffffccd8d28"
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- alias ["x21" ] = "s5"
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-
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- values ["s6" ] = "0x000000000014ddf8"
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- alias ["x22" ] = "s6"
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-
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- values ["s7" ] = "0x00ffffff99c69d48"
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- alias ["x23" ] = "s7"
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-
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- values ["s8" ] = "0x00ffffff99c6a008"
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- alias ["x24" ] = "s8"
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-
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- values ["s9" ] = "0x0"
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- alias ["x25" ] = "s9"
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-
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- values ["s10" ] = "0x0"
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- alias ["x26" ] = "s10"
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-
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- values ["s11" ] = "0x0"
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- alias ["x27" ] = "s11"
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-
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- values ["t3" ] = "0x00ffffff99c42000"
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- alias ["x28" ] = "t3"
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-
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- values ["t4" ] = "0x00ffffff99af8e20"
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- alias ["x29" ] = "t4"
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-
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- values ["t5" ] = "0x0000000000000005"
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- alias ["x30" ] = "t5"
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-
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- values ["t6" ] = "0x44760bdd8d5f6381"
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- alias ["x31" ] = "t6"
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-
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- values ["zero" ] = "0x0"
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- alias ["x0" ] = "zero"
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+ values = {
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+ "pc" : ( "0x0000000000010164" , None ),
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+ "zero" : ( "0x0" , "x0" ),
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+ "ra" : ( "0x0000000000010194" , "x1" ),
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+ "sp" : ( "0x00fffffff4d5fcc0" , "x2" ),
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+ "gp" : ( "0x0000000000157678" , "x3" ),
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+ "tp" : ( "0x00ffffff99c43400" , "x4" ),
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+ "t0" : ( "0x00ffffff99c6b260" , "x5" ),
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+ "t1" : ( "0x00ffffff99b7bd54" , "x6" ),
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+ "t2" : ( "0x0000000003f0b27f" , "x7" ),
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+ "fp" : ( "0x00fffffff4d5fcf0" , "x8" ),
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+ "s1" : ( "0x0000000000000003" , "x9" ),
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+ "a0" : ( "0x0" , "x10" ),
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+ "a1" : ( "0x0000000000010144" , "x11" ),
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+ "a2" : ( "0x0000000000176460" , "x12" ),
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+ "a3" : ( "0x000000000015ee38" , "x13" ),
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+ "a4" : ( "0x00000000423c0000" , "x14" ),
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+ "a5" : ( "0x0" , "x15" ),
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+ "a6" : ( "0x0" , "x16" ),
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+ "a7" : ( "0x00000000000000dd" , "x17" ),
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+ "s2" : ( "0x0" , "x18" ),
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+ "s3" : ( "0x000000000014ddf8" , "x19" ),
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+ "s4" : ( "0x000000000003651c" , "x20" ),
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+ "s5" : ( "0x00fffffffccd8d28" , "x21" ),
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+ "s6" : ( "0x000000000014ddf8" , "x22" ),
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+ "s7" : ( "0x00ffffff99c69d48" , "x23" ),
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+ "s8" : ( "0x00ffffff99c6a008" , "x24" ),
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+ "s9" : ( "0x0" , "x25" ),
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+ "s10" : ( "0x0" , "x26" ),
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+ "s11" : ( "0x0" , "x27" ),
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+ "t3" : ( "0x00ffffff99c42000" , "x28" ),
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+ "t4" : ( "0x00ffffff99af8e20" , "x29" ),
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+ "t5" : ( "0x0000000000000005" , "x30" ),
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+ "t6" : ( "0x44760bdd8d5f6381" , "x31" ),
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+ }
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- for regname , value in values .items ():
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+ for regname in values :
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+ value , alias = values [regname ]
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self .expect (
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"register read {}" .format (regname ),
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substrs = ["{} = {}" .format (regname , value )],
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)
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-
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- for aliasname , regname in alias .items ():
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- value = values [regname ]
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- self .expect (
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- "register read {}" .format (aliasname ),
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- substrs = ["{} = {}" .format (regname , value )],
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- )
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+ if alias :
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+ self .expect (
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+ "register read {}" .format (alias ),
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+ substrs = ["{} = {}" .format (regname , value )],
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+ )
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# Check that LLDB does not try to read other registers from core file
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self .expect (
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