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arsenmarsenm
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AMDGPU: Add some tests for folding immediates into subregister uses (#129663)
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‎llvm/test/CodeGen/AMDGPU/fold-operands-frame-index.mir

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@@ -393,3 +393,37 @@ body: |
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SI_RETURN implicit $vgpr0, implicit $vgpr1
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...
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---
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name: fold_frame_index__through_reg_sequence_to_user_subreg
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 4
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localFrameSize: 16384
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stack:
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- { id: 0, size: 16384, alignment: 4, local-offset: 0 }
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body: |
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bb.0:
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liveins: $sgpr8
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; CHECK-LABEL: name: fold_frame_index__through_reg_sequence_to_user_subreg
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; CHECK: liveins: $sgpr8
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr8
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 123
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; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 %stack.0
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
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; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], %stack.0, implicit-def $scc
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; CHECK-NEXT: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], 123, implicit-def $scc
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; CHECK-NEXT: $sgpr4 = COPY [[S_ADD_I32_]]
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; CHECK-NEXT: $sgpr5 = COPY [[S_ADD_I32_1]]
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; CHECK-NEXT: SI_RETURN implicit $sgpr4, implicit $sgpr5
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%0:sreg_32 = COPY $sgpr8
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%1:sreg_32 = S_MOV_B32 123
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%2:sreg_32 = S_MOV_B32 %stack.0
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%3:sreg_64 = REG_SEQUENCE %1, %subreg.sub0, %2, %subreg.sub1
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%4:sreg_32 = S_ADD_I32 %0, %3.sub1, implicit-def $scc
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%5:sreg_32 = S_ADD_I32 %0, %3.sub0, implicit-def $scc
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$sgpr4 = COPY %4
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$sgpr5 = COPY %5
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SI_RETURN implicit $sgpr4, implicit $sgpr5
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...

‎llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=si-fold-operands -o - %s | FileCheck %s
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# Make sure materializes of 64-bit immediates fold the correct value
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# into subregister uses.
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---
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name: s_mov_b64_sub1_folds_wrong_value_0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr8_sgpr9
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; CHECK-LABEL: name: s_mov_b64_sub1_folds_wrong_value_0
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; CHECK: liveins: $sgpr8_sgpr9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[COPY]].sub1, %subreg.sub1
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; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[REG_SEQUENCE]].sub0, 8, implicit-def $scc
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; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[REG_SEQUENCE]].sub1, 8, implicit-def $scc, implicit $scc
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; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
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; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
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%0:sgpr_64 = COPY $sgpr8_sgpr9
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%1:sreg_64 = REG_SEQUENCE %0.sub0, %subreg.sub0, %0.sub1, %subreg.sub1
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%2:sreg_64 = S_MOV_B64 8
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%3:sreg_32 = S_ADD_U32 %1.sub0, %2.sub0, implicit-def $scc
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%4:sreg_32 = S_ADDC_U32 %1.sub1, %2.sub1, implicit-def $scc, implicit $scc
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%5:sreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
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S_ENDPGM 0, implicit %5
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...
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---
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name: v_mov_b64_pseudo_sub1_folds_wrong_value
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr8_vgpr9
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; CHECK-LABEL: name: v_mov_b64_pseudo_sub1_folds_wrong_value
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; CHECK: liveins: $vgpr8_vgpr9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr8_vgpr9
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[COPY]].sub1, %subreg.sub1
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; CHECK-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[REG_SEQUENCE]].sub0, 30064771075, 0, implicit $exec
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; CHECK-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[REG_SEQUENCE]].sub1, 30064771075, [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
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; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, [[V_ADDC_U32_e64_]], %subreg.sub1
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; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
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%0:vreg_64 = COPY $vgpr8_vgpr9
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%1:vreg_64 = REG_SEQUENCE %0.sub0, %subreg.sub0, %0.sub1, %subreg.sub1
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%2:vreg_64 = V_MOV_B64_PSEUDO 30064771075, implicit $exec
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%3:vgpr_32, %6:sreg_64_xexec = V_ADD_CO_U32_e64 %1.sub0, %2.sub0, 0, implicit $exec
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%4:vgpr_32, %7:sreg_64_xexec = V_ADDC_U32_e64 %1.sub1, %2.sub1, %6, 0, implicit $exec
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%5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1
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S_ENDPGM 0, implicit %5
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...
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---
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name: subreg_fold_imm
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr8_sgpr9, $vgpr8_vgpr9
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; CHECK-LABEL: name: subreg_fold_imm
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; CHECK: liveins: $sgpr8_sgpr9, $vgpr8_vgpr9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[COPY]].sub1, %subreg.sub1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]]
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; CHECK-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[REG_SEQUENCE]].sub1, [[COPY1]].sub1, 0, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
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%0:sgpr_64 = COPY $sgpr8_sgpr9
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%1:sreg_64 = REG_SEQUENCE %0.sub0, %subreg.sub0, %0.sub1, %subreg.sub1
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%2:vreg_64 = COPY %0
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%3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 %1.sub1, %2.sub1, 0, implicit $exec
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S_ENDPGM 0, implicit %3
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...
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---
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name: s_mov_b64_into_reg_sequence_user
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr8_sgpr9
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; CHECK-LABEL: name: s_mov_b64_into_reg_sequence_user
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; CHECK: liveins: $sgpr8_sgpr9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 8
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B64_]].sub1, %subreg.sub0, [[S_MOV_B64_]].sub0, %subreg.sub1
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; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[REG_SEQUENCE]], implicit-def $scc
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; CHECK-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]
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%0:sgpr_64 = COPY $sgpr8_sgpr9
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%1:sreg_64 = S_MOV_B64 8
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%2:sreg_64 = REG_SEQUENCE %1.sub1, %subreg.sub0, %1.sub0, %subreg.sub1
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%3:sreg_64 = S_AND_B64 %0, %2, implicit-def $scc
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S_ENDPGM 0, implicit %3
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...
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---
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name: s_mov_b64_into_reg_sequence_user_with_subregs
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr8_sgpr9
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; CHECK-LABEL: name: s_mov_b64_into_reg_sequence_user_with_subregs
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; CHECK: liveins: $sgpr8_sgpr9
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 8
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B64_]].sub1, %subreg.sub0, [[S_MOV_B64_]].sub0, %subreg.sub1
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; CHECK-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]].sub0, 8, implicit-def $scc
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; CHECK-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY]].sub1, 8, implicit-def $scc, implicit $scc
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; CHECK-NEXT: S_ENDPGM 0, implicit [[S_ADD_U32_]], implicit [[S_ADDC_U32_]]
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%0:sgpr_64 = COPY $sgpr8_sgpr9
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%1:sreg_64 = S_MOV_B64 8
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%2:sreg_64 = REG_SEQUENCE %1.sub1, %subreg.sub0, %1.sub0, %subreg.sub1
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%3:sreg_32 = S_ADD_U32 %0.sub0, %2.sub0, implicit-def $scc
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%4:sreg_32 = S_ADDC_U32 %0.sub1, %2.sub1, implicit-def $scc, implicit $scc
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S_ENDPGM 0, implicit %3, implicit %4
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...
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