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[RISCV][GISel] Add instruction selection for G_FADD/G_FSUB/G_FMUL/G_FDIV with F/D extensions.
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‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

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Original file line numberDiff line numberDiff line change
@@ -450,6 +450,13 @@ const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
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return &RISCV::GPRRegClass;
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}
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if (RB.getID() == RISCV::FPRRegBankID) {
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if (Ty.getSizeInBits() == 32)
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return &RISCV::FPR32RegClass;
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if (Ty.getSizeInBits() == 64)
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return &RISCV::FPR64RegClass;
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}
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// TODO: Non-GPR register classes.
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return nullptr;
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}

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith.mir

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@@ -0,0 +1,198 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: fadd_f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_f, $f11_f
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; CHECK-LABEL: name: fadd_f32
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; CHECK: liveins: $f10_f, $f11_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
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; CHECK-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_f = COPY [[FADD_S]]
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; CHECK-NEXT: PseudoRET implicit $f10_f
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%0:fprb(s32) = COPY $f10_f
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%1:fprb(s32) = COPY $f11_f
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%2:fprb(s32) = G_FADD %0, %1
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$f10_f = COPY %2(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: fsub_f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_f, $f11_f
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; CHECK-LABEL: name: fsub_f32
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; CHECK: liveins: $f10_f, $f11_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
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; CHECK-NEXT: [[FSUB_S:%[0-9]+]]:fpr32 = nofpexcept FSUB_S [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_f = COPY [[FSUB_S]]
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; CHECK-NEXT: PseudoRET implicit $f10_f
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%0:fprb(s32) = COPY $f10_f
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%1:fprb(s32) = COPY $f11_f
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%2:fprb(s32) = G_FSUB %0, %1
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$f10_f = COPY %2(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: fmul_f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_f, $f11_f
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; CHECK-LABEL: name: fmul_f32
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; CHECK: liveins: $f10_f, $f11_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
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; CHECK-NEXT: [[FMUL_S:%[0-9]+]]:fpr32 = nofpexcept FMUL_S [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_f = COPY [[FMUL_S]]
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; CHECK-NEXT: PseudoRET implicit $f10_f
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%0:fprb(s32) = COPY $f10_f
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%1:fprb(s32) = COPY $f11_f
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%2:fprb(s32) = G_FMUL %0, %1
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$f10_f = COPY %2(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: fdiv_f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_f, $f11_f
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; CHECK-LABEL: name: fdiv_f32
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; CHECK: liveins: $f10_f, $f11_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
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; CHECK-NEXT: [[FDIV_S:%[0-9]+]]:fpr32 = nofpexcept FDIV_S [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_f = COPY [[FDIV_S]]
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; CHECK-NEXT: PseudoRET implicit $f10_f
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%0:fprb(s32) = COPY $f10_f
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%1:fprb(s32) = COPY $f11_f
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%2:fprb(s32) = G_FDIV %0, %1
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$f10_f = COPY %2(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: fadd_f64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_d, $f11_d
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; CHECK-LABEL: name: fadd_f64
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; CHECK: liveins: $f10_d, $f11_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
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; CHECK-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_d = COPY [[FADD_D]]
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; CHECK-NEXT: PseudoRET implicit $f10_d
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%0:fprb(s64) = COPY $f10_d
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%1:fprb(s64) = COPY $f11_d
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%2:fprb(s64) = G_FADD %0, %1
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$f10_d = COPY %2(s64)
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PseudoRET implicit $f10_d
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...
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---
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name: fsub_f64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_d, $f11_d
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; CHECK-LABEL: name: fsub_f64
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; CHECK: liveins: $f10_d, $f11_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
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; CHECK-NEXT: [[FSUB_D:%[0-9]+]]:fpr64 = nofpexcept FSUB_D [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_d = COPY [[FSUB_D]]
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; CHECK-NEXT: PseudoRET implicit $f10_d
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%0:fprb(s64) = COPY $f10_d
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%1:fprb(s64) = COPY $f11_d
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%2:fprb(s64) = G_FSUB %0, %1
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$f10_d = COPY %2(s64)
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PseudoRET implicit $f10_d
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...
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---
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name: fmul_f64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_d, $f11_d
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; CHECK-LABEL: name: fmul_f64
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; CHECK: liveins: $f10_d, $f11_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
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; CHECK-NEXT: [[FMUL_D:%[0-9]+]]:fpr64 = nofpexcept FMUL_D [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_d = COPY [[FMUL_D]]
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; CHECK-NEXT: PseudoRET implicit $f10_d
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%0:fprb(s64) = COPY $f10_d
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%1:fprb(s64) = COPY $f11_d
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%2:fprb(s64) = G_FMUL %0, %1
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$f10_d = COPY %2(s64)
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PseudoRET implicit $f10_d
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...
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---
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name: fdiv_f64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $f10_d, $f11_d
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; CHECK-LABEL: name: fdiv_f64
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; CHECK: liveins: $f10_d, $f11_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $f11_d
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; CHECK-NEXT: [[FDIV_D:%[0-9]+]]:fpr64 = nofpexcept FDIV_D [[COPY]], [[COPY1]], 7
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; CHECK-NEXT: $f10_d = COPY [[FDIV_D]]
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; CHECK-NEXT: PseudoRET implicit $f10_d
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%0:fprb(s64) = COPY $f10_d
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%1:fprb(s64) = COPY $f11_d
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%2:fprb(s64) = G_FDIV %0, %1
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$f10_d = COPY %2(s64)
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PseudoRET implicit $f10_d
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...

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