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Change getCopyMapping to take a TypeSize
1 parent c960a6e commit 02a9229

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3 files changed

+44
-35
lines changed

3 files changed

+44
-35
lines changed

‎llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def

Lines changed: 16 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,9 @@ bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
137137
unsigned Offset) {
138138
unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
139139
const ValueMapping &Map =
140-
AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
140+
AArch64GenRegisterBankInfo::getValueMapping(
141+
(PartialMappingIdx)FirstInBank,
142+
TypeSize::getFixed(Size))[Offset];
141143
return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
142144
Map.NumBreakDowns == 1;
143145
}
@@ -167,7 +169,7 @@ bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
167169
}
168170

169171
unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
170-
unsigned Size) {
172+
TypeSize Size) {
171173
if (RBIdx == PMI_FirstGPR) {
172174
if (Size <= 32)
173175
return 0;
@@ -178,17 +180,20 @@ unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
178180
return -1;
179181
}
180182
if (RBIdx == PMI_FirstFPR) {
181-
if (Size <= 16)
183+
const unsigned MinSize = Size.getKnownMinValue();
184+
assert(!Size.isScalable() || MinSize >= 128
185+
&& "Scalable vector types should have size of at least 128 bits");
186+
if (MinSize <= 16)
182187
return 0;
183-
if (Size <= 32)
188+
if (MinSize <= 32)
184189
return 1;
185-
if (Size <= 64)
190+
if (MinSize <= 64)
186191
return 2;
187-
if (Size <= 128)
192+
if (MinSize <= 128)
188193
return 3;
189-
if (Size <= 256)
194+
if (MinSize <= 256)
190195
return 4;
191-
if (Size <= 512)
196+
if (MinSize <= 512)
192197
return 5;
193198
return -1;
194199
}
@@ -197,7 +202,7 @@ unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
197202

198203
const RegisterBankInfo::ValueMapping *
199204
AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
200-
unsigned Size) {
205+
const TypeSize Size) {
201206
assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
202207
unsigned BaseIdxOffset = getRegBankBaseIdxOffset(RBIdx, Size);
203208
if (BaseIdxOffset == -1u)
@@ -221,7 +226,8 @@ const AArch64GenRegisterBankInfo::PartialMappingIdx
221226

222227
const RegisterBankInfo::ValueMapping *
223228
AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID,
224-
unsigned SrcBankID, unsigned Size) {
229+
unsigned SrcBankID,
230+
const TypeSize Size) {
225231
assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
226232
assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
227233
PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Lines changed: 25 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -163,17 +163,18 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(
163163
unsigned PartialMapSrcIdx = PMI_##RBNameSrc##Size - PMI_Min; \
164164
(void)PartialMapDstIdx; \
165165
(void)PartialMapSrcIdx; \
166-
const ValueMapping *Map = getCopyMapping( \
167-
AArch64::RBNameDst##RegBankID, AArch64::RBNameSrc##RegBankID, Size); \
166+
const ValueMapping *Map = getCopyMapping(AArch64::RBNameDst##RegBankID, \
167+
AArch64::RBNameSrc##RegBankID, \
168+
TypeSize::getFixed(Size)); \
168169
(void)Map; \
169170
assert(Map[0].BreakDown == \
170171
&AArch64GenRegisterBankInfo::PartMappings[PartialMapDstIdx] && \
171-
Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
172-
" Dst is incorrectly initialized"); \
172+
Map[0].NumBreakDowns == 1 && \
173+
#RBNameDst #Size " Dst is incorrectly initialized"); \
173174
assert(Map[1].BreakDown == \
174175
&AArch64GenRegisterBankInfo::PartMappings[PartialMapSrcIdx] && \
175-
Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
176-
" Src is incorrectly initialized"); \
176+
Map[1].NumBreakDowns == 1 && \
177+
#RBNameSrc #Size " Src is incorrectly initialized"); \
177178
\
178179
} while (false)
179180

@@ -218,7 +219,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(
218219

219220
unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,
220221
const RegisterBank &B,
221-
TypeSize Size) const {
222+
const TypeSize Size) const {
222223
// What do we do with different size?
223224
// copy are same size.
224225
// Will introduce other hooks for different size:
@@ -305,7 +306,7 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
305306
case TargetOpcode::G_OR: {
306307
// 32 and 64-bit or can be mapped on either FPR or
307308
// GPR for the same cost.
308-
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
309+
TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
309310
if (Size != 32 && Size != 64)
310311
break;
311312

@@ -326,7 +327,7 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
326327
return AltMappings;
327328
}
328329
case TargetOpcode::G_BITCAST: {
329-
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
330+
TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
330331
if (Size != 32 && Size != 64)
331332
break;
332333

@@ -366,7 +367,7 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
366367
return AltMappings;
367368
}
368369
case TargetOpcode::G_LOAD: {
369-
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
370+
TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
370371
if (Size != 64)
371372
break;
372373

@@ -378,15 +379,17 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings(
378379
InstructionMappings AltMappings;
379380
const InstructionMapping &GPRMapping = getInstructionMapping(
380381
/*ID*/ 1, /*Cost*/ 1,
381-
getOperandsMapping({getValueMapping(PMI_FirstGPR, Size),
382-
// Addresses are GPR 64-bit.
383-
getValueMapping(PMI_FirstGPR, 64)}),
382+
getOperandsMapping(
383+
{getValueMapping(PMI_FirstGPR, Size),
384+
// Addresses are GPR 64-bit.
385+
getValueMapping(PMI_FirstGPR, TypeSize::getFixed(64))}),
384386
/*NumOperands*/ 2);
385387
const InstructionMapping &FPRMapping = getInstructionMapping(
386388
/*ID*/ 2, /*Cost*/ 1,
387-
getOperandsMapping({getValueMapping(PMI_FirstFPR, Size),
388-
// Addresses are GPR 64-bit.
389-
getValueMapping(PMI_FirstGPR, 64)}),
389+
getOperandsMapping(
390+
{getValueMapping(PMI_FirstFPR, Size),
391+
// Addresses are GPR 64-bit.
392+
getValueMapping(PMI_FirstGPR, TypeSize::getFixed(64))}),
390393
/*NumOperands*/ 2);
391394

392395
AltMappings.push_back(&GPRMapping);
@@ -438,7 +441,7 @@ AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
438441
"This code is for instructions with 3 or less operands");
439442

440443
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
441-
unsigned Size = Ty.getSizeInBits();
444+
TypeSize Size = Ty.getSizeInBits();
442445
bool IsFPR = Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
443446

444447
PartialMappingIdx RBIdx = IsFPR ? PMI_FirstFPR : PMI_FirstGPR;
@@ -718,8 +721,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
718721
TypeSize Size = getSizeInBits(DstReg, MRI, TRI);
719722
return getInstructionMapping(
720723
DefaultMappingID, copyCost(*DstRB, *SrcRB, Size),
721-
getCopyMapping(DstRB->getID(), SrcRB->getID(),
722-
Size.getKnownMinValue()),
724+
getCopyMapping(DstRB->getID(), SrcRB->getID(), Size),
723725
// We only care about the mapping of the destination.
724726
/*NumOperands*/ 1);
725727
}
@@ -729,15 +731,15 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
729731
case TargetOpcode::G_BITCAST: {
730732
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
731733
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
732-
unsigned Size = DstTy.getSizeInBits();
734+
TypeSize Size = DstTy.getSizeInBits();
733735
bool DstIsGPR = !DstTy.isVector() && DstTy.getSizeInBits() <= 64;
734736
bool SrcIsGPR = !SrcTy.isVector() && SrcTy.getSizeInBits() <= 64;
735737
const RegisterBank &DstRB =
736738
DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
737739
const RegisterBank &SrcRB =
738740
SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
739741
return getInstructionMapping(
740-
DefaultMappingID, copyCost(DstRB, SrcRB, TypeSize::getFixed(Size)),
742+
DefaultMappingID, copyCost(DstRB, SrcRB, Size),
741743
getCopyMapping(DstRB.getID(), SrcRB.getID(), Size),
742744
// We only care about the mapping of the destination for COPY.
743745
/*NumOperands*/ Opc == TargetOpcode::G_BITCAST ? 2 : 1);
@@ -1128,7 +1130,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
11281130
LLT Ty = MRI.getType(MI.getOperand(Idx).getReg());
11291131
if (!Ty.isValid())
11301132
continue;
1131-
auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
1133+
auto Mapping =
1134+
getValueMapping(OpRegBankIdx[Idx], TypeSize::getFixed(OpSize[Idx]));
11321135
if (!Mapping->isValid())
11331136
return getInvalidInstructionMapping();
11341137

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ class AArch64GenRegisterBankInfo : public RegisterBankInfo {
7070
PartialMappingIdx LastAlias,
7171
ArrayRef<PartialMappingIdx> Order);
7272

73-
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
73+
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, TypeSize Size);
7474

7575
/// Get the pointer to the ValueMapping representing the RegisterBank
7676
/// at \p RBIdx with a size of \p Size.
@@ -80,13 +80,13 @@ class AArch64GenRegisterBankInfo : public RegisterBankInfo {
8080
///
8181
/// \pre \p RBIdx != PartialMappingIdx::None
8282
static const RegisterBankInfo::ValueMapping *
83-
getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
83+
getValueMapping(PartialMappingIdx RBIdx, TypeSize Size);
8484

8585
/// Get the pointer to the ValueMapping of the operands of a copy
8686
/// instruction from the \p SrcBankID register bank to the \p DstBankID
8787
/// register bank with a size of \p Size.
8888
static const RegisterBankInfo::ValueMapping *
89-
getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
89+
getCopyMapping(unsigned DstBankID, unsigned SrcBankID, TypeSize Size);
9090

9191
/// Get the instruction mapping for G_FPEXT.
9292
///

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