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[X86] AMD Zen 5 Initial enablement (#107964)
This patch enables the basic skeleton enablement of AMD next gen zen5 CPUs.
1 parent fffc7fb commit 02e4186

30 files changed

+238
-0
lines changed

‎clang/lib/Basic/Targets/X86.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -728,6 +728,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
728728
case CK_ZNVER4:
729729
defineCPUMacros(Builder, "znver4");
730730
break;
731+
case CK_ZNVER5:
732+
defineCPUMacros(Builder, "znver5");
733+
break;
731734
case CK_Geode:
732735
defineCPUMacros(Builder, "geode");
733736
break;
@@ -1626,6 +1629,7 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
16261629
case CK_ZNVER2:
16271630
case CK_ZNVER3:
16281631
case CK_ZNVER4:
1632+
case CK_ZNVER5:
16291633
// Deprecated
16301634
case CK_x86_64:
16311635
case CK_x86_64_v2:

‎clang/test/CodeGen/target-builtin-noerror.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,4 +207,5 @@ void verifycpustrings(void) {
207207
(void)__builtin_cpu_is("znver2");
208208
(void)__builtin_cpu_is("znver3");
209209
(void)__builtin_cpu_is("znver4");
210+
(void)__builtin_cpu_is("znver5");
210211
}

‎clang/test/Driver/x86-march.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -242,6 +242,10 @@
242242
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver4 2>&1 \
243243
// RUN: | FileCheck %s -check-prefix=znver4
244244
// znver4: "-target-cpu" "znver4"
245+
//
246+
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=znver5 2>&1 \
247+
// RUN: | FileCheck %s -check-prefix=znver5
248+
// znver5: "-target-cpu" "znver5"
245249

246250
// RUN: %clang -target x86_64 -c -### %s -march=x86-64 2>&1 | FileCheck %s --check-prefix=x86-64
247251
// x86-64: "-target-cpu" "x86-64"

‎clang/test/Frontend/x86-target-cpu.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,5 +38,6 @@
3838
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver2 -verify %s
3939
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver3 -verify %s
4040
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver4 -verify %s
41+
// RUN: %clang_cc1 -triple x86_64-unknown-unknown -target-cpu znver5 -verify %s
4142
//
4243
// expected-no-diagnostics

‎clang/test/Misc/target-invalid-cpu-note/x86.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,7 @@
9999
// X86-SAME: {{^}}, znver2
100100
// X86-SAME: {{^}}, znver3
101101
// X86-SAME: {{^}}, znver4
102+
// X86-SAME: {{^}}, znver5
102103
// X86-SAME: {{^}}, x86-64
103104
// X86-SAME: {{^}}, x86-64-v2
104105
// X86-SAME: {{^}}, x86-64-v3
@@ -175,6 +176,7 @@
175176
// X86_64-SAME: {{^}}, znver2
176177
// X86_64-SAME: {{^}}, znver3
177178
// X86_64-SAME: {{^}}, znver4
179+
// X86_64-SAME: {{^}}, znver5
178180
// X86_64-SAME: {{^}}, x86-64
179181
// X86_64-SAME: {{^}}, x86-64-v2
180182
// X86_64-SAME: {{^}}, x86-64-v3
@@ -278,6 +280,7 @@
278280
// TUNE_X86-SAME: {{^}}, znver2
279281
// TUNE_X86-SAME: {{^}}, znver3
280282
// TUNE_X86-SAME: {{^}}, znver4
283+
// TUNE_X86-SAME: {{^}}, znver5
281284
// TUNE_X86-SAME: {{^}}, x86-64
282285
// TUNE_X86-SAME: {{^}}, geode
283286
// TUNE_X86-SAME: {{$}}
@@ -379,6 +382,7 @@
379382
// TUNE_X86_64-SAME: {{^}}, znver2
380383
// TUNE_X86_64-SAME: {{^}}, znver3
381384
// TUNE_X86_64-SAME: {{^}}, znver4
385+
// TUNE_X86_64-SAME: {{^}}, znver5
382386
// TUNE_X86_64-SAME: {{^}}, x86-64
383387
// TUNE_X86_64-SAME: {{^}}, geode
384388
// TUNE_X86_64-SAME: {{$}}

‎clang/test/Preprocessor/predefined-arch-macros.c

Lines changed: 142 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3923,6 +3923,148 @@
39233923
// CHECK_ZNVER4_M64: #define __znver4 1
39243924
// CHECK_ZNVER4_M64: #define __znver4__ 1
39253925

3926+
// RUN: %clang -march=znver5 -m32 -E -dM %s -o - 2>&1 \
3927+
// RUN: -target i386-unknown-linux \
3928+
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER5_M32
3929+
// CHECK_ZNVER5_M32-NOT: #define __3dNOW_A__ 1
3930+
// CHECK_ZNVER5_M32-NOT: #define __3dNOW__ 1
3931+
// CHECK_ZNVER5_M32: #define __ADX__ 1
3932+
// CHECK_ZNVER5_M32: #define __AES__ 1
3933+
// CHECK_ZNVER5_M32: #define __AVX2__ 1
3934+
// CHECK_ZNVER5_M32: #define __AVX512BF16__ 1
3935+
// CHECK_ZNVER5_M32: #define __AVX512BITALG__ 1
3936+
// CHECK_ZNVER5_M32: #define __AVX512BW__ 1
3937+
// CHECK_ZNVER5_M32: #define __AVX512CD__ 1
3938+
// CHECK_ZNVER5_M32: #define __AVX512DQ__ 1
3939+
// CHECK_ZNVER5_M32: #define __AVX512F__ 1
3940+
// CHECK_ZNVER5_M32: #define __AVX512IFMA__ 1
3941+
// CHECK_ZNVER5_M32: #define __AVX512VBMI2__ 1
3942+
// CHECK_ZNVER5_M32: #define __AVX512VBMI__ 1
3943+
// CHECK_ZNVER5_M32: #define __AVX512VL__ 1
3944+
// CHECK_ZNVER5_M32: #define __AVX512VNNI__ 1
3945+
// CHECK_ZNVER5_M32: #define __AVX512VP2INTERSECT__ 1
3946+
// CHECK_ZNVER5_M32: #define __AVX512VPOPCNTDQ__ 1
3947+
// CHECK_ZNVER5_M32: #define __AVXVNNI__ 1
3948+
// CHECK_ZNVER5_M32: #define __AVX__ 1
3949+
// CHECK_ZNVER5_M32: #define __BMI2__ 1
3950+
// CHECK_ZNVER5_M32: #define __BMI__ 1
3951+
// CHECK_ZNVER5_M32: #define __CLFLUSHOPT__ 1
3952+
// CHECK_ZNVER5_M32: #define __CLWB__ 1
3953+
// CHECK_ZNVER5_M32: #define __CLZERO__ 1
3954+
// CHECK_ZNVER5_M32: #define __F16C__ 1
3955+
// CHECK_ZNVER5_M32-NOT: #define __FMA4__ 1
3956+
// CHECK_ZNVER5_M32: #define __FMA__ 1
3957+
// CHECK_ZNVER5_M32: #define __FSGSBASE__ 1
3958+
// CHECK_ZNVER5_M32: #define __GFNI__ 1
3959+
// CHECK_ZNVER5_M32: #define __LZCNT__ 1
3960+
// CHECK_ZNVER5_M32: #define __MMX__ 1
3961+
// CHECK_ZNVER5_M32: #define __MOVDIR64B__ 1
3962+
// CHECK_ZNVER5_M32: #define __MOVDIRI__ 1
3963+
// CHECK_ZNVER5_M32: #define __PCLMUL__ 1
3964+
// CHECK_ZNVER5_M32: #define __PKU__ 1
3965+
// CHECK_ZNVER5_M32: #define __POPCNT__ 1
3966+
// CHECK_ZNVER5_M32: #define __PREFETCHI__ 1
3967+
// CHECK_ZNVER5_M32: #define __PRFCHW__ 1
3968+
// CHECK_ZNVER5_M32: #define __RDPID__ 1
3969+
// CHECK_ZNVER5_M32: #define __RDPRU__ 1
3970+
// CHECK_ZNVER5_M32: #define __RDRND__ 1
3971+
// CHECK_ZNVER5_M32: #define __RDSEED__ 1
3972+
// CHECK_ZNVER5_M32: #define __SHA__ 1
3973+
// CHECK_ZNVER5_M32: #define __SSE2_MATH__ 1
3974+
// CHECK_ZNVER5_M32: #define __SSE2__ 1
3975+
// CHECK_ZNVER5_M32: #define __SSE3__ 1
3976+
// CHECK_ZNVER5_M32: #define __SSE4A__ 1
3977+
// CHECK_ZNVER5_M32: #define __SSE4_1__ 1
3978+
// CHECK_ZNVER5_M32: #define __SSE4_2__ 1
3979+
// CHECK_ZNVER5_M32: #define __SSE_MATH__ 1
3980+
// CHECK_ZNVER5_M32: #define __SSE__ 1
3981+
// CHECK_ZNVER5_M32: #define __SSSE3__ 1
3982+
// CHECK_ZNVER5_M32-NOT: #define __TBM__ 1
3983+
// CHECK_ZNVER5_M32: #define __WBNOINVD__ 1
3984+
// CHECK_ZNVER5_M32-NOT: #define __XOP__ 1
3985+
// CHECK_ZNVER5_M32: #define __XSAVEC__ 1
3986+
// CHECK_ZNVER5_M32: #define __XSAVEOPT__ 1
3987+
// CHECK_ZNVER5_M32: #define __XSAVES__ 1
3988+
// CHECK_ZNVER5_M32: #define __XSAVE__ 1
3989+
// CHECK_ZNVER5_M32: #define __i386 1
3990+
// CHECK_ZNVER5_M32: #define __i386__ 1
3991+
// CHECK_ZNVER5_M32: #define __tune_znver5__ 1
3992+
// CHECK_ZNVER5_M32: #define __znver5 1
3993+
// CHECK_ZNVER5_M32: #define __znver5__ 1
3994+
3995+
// RUN: %clang -march=znver5 -m64 -E -dM %s -o - 2>&1 \
3996+
// RUN: -target i386-unknown-linux \
3997+
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER5_M64
3998+
// CHECK_ZNVER5_M64-NOT: #define __3dNOW_A__ 1
3999+
// CHECK_ZNVER5_M64-NOT: #define __3dNOW__ 1
4000+
// CHECK_ZNVER5_M64: #define __ADX__ 1
4001+
// CHECK_ZNVER5_M64: #define __AES__ 1
4002+
// CHECK_ZNVER5_M64: #define __AVX2__ 1
4003+
// CHECK_ZNVER5_M64: #define __AVX512BF16__ 1
4004+
// CHECK_ZNVER5_M64: #define __AVX512BITALG__ 1
4005+
// CHECK_ZNVER5_M64: #define __AVX512BW__ 1
4006+
// CHECK_ZNVER5_M64: #define __AVX512CD__ 1
4007+
// CHECK_ZNVER5_M64: #define __AVX512DQ__ 1
4008+
// CHECK_ZNVER5_M64: #define __AVX512F__ 1
4009+
// CHECK_ZNVER5_M64: #define __AVX512IFMA__ 1
4010+
// CHECK_ZNVER5_M64: #define __AVX512VBMI2__ 1
4011+
// CHECK_ZNVER5_M64: #define __AVX512VBMI__ 1
4012+
// CHECK_ZNVER5_M64: #define __AVX512VL__ 1
4013+
// CHECK_ZNVER5_M64: #define __AVX512VNNI__ 1
4014+
// CHECK_ZNVER5_M64: #define __AVX512VP2INTERSECT__ 1
4015+
// CHECK_ZNVER5_M64: #define __AVX512VPOPCNTDQ__ 1
4016+
// CHECK_ZNVER5_M64: #define __AVXVNNI__ 1
4017+
// CHECK_ZNVER5_M64: #define __AVX__ 1
4018+
// CHECK_ZNVER5_M64: #define __BMI2__ 1
4019+
// CHECK_ZNVER5_M64: #define __BMI__ 1
4020+
// CHECK_ZNVER5_M64: #define __CLFLUSHOPT__ 1
4021+
// CHECK_ZNVER5_M64: #define __CLWB__ 1
4022+
// CHECK_ZNVER5_M64: #define __CLZERO__ 1
4023+
// CHECK_ZNVER5_M64: #define __F16C__ 1
4024+
// CHECK_ZNVER5_M64-NOT: #define __FMA4__ 1
4025+
// CHECK_ZNVER5_M64: #define __FMA__ 1
4026+
// CHECK_ZNVER5_M64: #define __FSGSBASE__ 1
4027+
// CHECK_ZNVER5_M64: #define __GFNI__ 1
4028+
// CHECK_ZNVER5_M64: #define __LZCNT__ 1
4029+
// CHECK_ZNVER5_M64: #define __MMX__ 1
4030+
// CHECK_ZNVER5_M64: #define __MOVDIR64B__ 1
4031+
// CHECK_ZNVER5_M64: #define __MOVDIRI__ 1
4032+
// CHECK_ZNVER5_M64: #define __PCLMUL__ 1
4033+
// CHECK_ZNVER5_M64: #define __PKU__ 1
4034+
// CHECK_ZNVER5_M64: #define __POPCNT__ 1
4035+
// CHECK_ZNVER5_M64: #define __PREFETCHI__ 1
4036+
// CHECK_ZNVER5_M64: #define __PRFCHW__ 1
4037+
// CHECK_ZNVER5_M64: #define __RDPID__ 1
4038+
// CHECK_ZNVER5_M64: #define __RDPRU__ 1
4039+
// CHECK_ZNVER5_M64: #define __RDRND__ 1
4040+
// CHECK_ZNVER5_M64: #define __RDSEED__ 1
4041+
// CHECK_ZNVER5_M64: #define __SHA__ 1
4042+
// CHECK_ZNVER5_M64: #define __SSE2_MATH__ 1
4043+
// CHECK_ZNVER5_M64: #define __SSE2__ 1
4044+
// CHECK_ZNVER5_M64: #define __SSE3__ 1
4045+
// CHECK_ZNVER5_M64: #define __SSE4A__ 1
4046+
// CHECK_ZNVER5_M64: #define __SSE4_1__ 1
4047+
// CHECK_ZNVER5_M64: #define __SSE4_2__ 1
4048+
// CHECK_ZNVER5_M64: #define __SSE_MATH__ 1
4049+
// CHECK_ZNVER5_M64: #define __SSE__ 1
4050+
// CHECK_ZNVER5_M64: #define __SSSE3__ 1
4051+
// CHECK_ZNVER5_M64-NOT: #define __TBM__ 1
4052+
// CHECK_ZNVER5_M64: #define __VAES__ 1
4053+
// CHECK_ZNVER5_M64: #define __VPCLMULQDQ__ 1
4054+
// CHECK_ZNVER5_M64: #define __WBNOINVD__ 1
4055+
// CHECK_ZNVER5_M64-NOT: #define __XOP__ 1
4056+
// CHECK_ZNVER5_M64: #define __XSAVEC__ 1
4057+
// CHECK_ZNVER5_M64: #define __XSAVEOPT__ 1
4058+
// CHECK_ZNVER5_M64: #define __XSAVES__ 1
4059+
// CHECK_ZNVER5_M64: #define __XSAVE__ 1
4060+
// CHECK_ZNVER5_M64: #define __amd64 1
4061+
// CHECK_ZNVER5_M64: #define __amd64__ 1
4062+
// CHECK_ZNVER5_M64: #define __tune_znver5__ 1
4063+
// CHECK_ZNVER5_M64: #define __x86_64 1
4064+
// CHECK_ZNVER5_M64: #define __x86_64__ 1
4065+
// CHECK_ZNVER5_M64: #define __znver5 1
4066+
// CHECK_ZNVER5_M64: #define __znver5__ 1
4067+
39264068
// End X86/GCC/Linux tests ------------------
39274069

39284070
// Begin PPC/GCC/Linux tests ----------------

‎compiler-rt/lib/builtins/cpu_model/x86.c

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,7 @@ enum ProcessorTypes {
6363
INTEL_SIERRAFOREST,
6464
INTEL_GRANDRIDGE,
6565
INTEL_CLEARWATERFOREST,
66+
AMDFAM1AH,
6667
CPU_TYPE_MAX
6768
};
6869

@@ -101,6 +102,7 @@ enum ProcessorSubtypes {
101102
INTEL_COREI7_ARROWLAKE,
102103
INTEL_COREI7_ARROWLAKE_S,
103104
INTEL_COREI7_PANTHERLAKE,
105+
AMDFAM1AH_ZNVER5,
104106
CPU_SUBTYPE_MAX
105107
};
106108

@@ -748,6 +750,24 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
748750
break; // "znver4"
749751
}
750752
break; // family 19h
753+
case 26:
754+
CPU = "znver5";
755+
*Type = AMDFAM1AH;
756+
if (Model <= 0x77) {
757+
// Models 00h-0Fh (Breithorn).
758+
// Models 10h-1Fh (Breithorn-Dense).
759+
// Models 20h-2Fh (Strix 1).
760+
// Models 30h-37h (Strix 2).
761+
// Models 38h-3Fh (Strix 3).
762+
// Models 40h-4Fh (Granite Ridge).
763+
// Models 50h-5Fh (Weisshorn).
764+
// Models 60h-6Fh (Krackan1).
765+
// Models 70h-77h (Sarlak).
766+
CPU = "znver5";
767+
*Subtype = AMDFAM1AH_ZNVER5;
768+
break; // "znver5"
769+
}
770+
break;
751771
default:
752772
break; // Unknown AMD CPU.
753773
}

‎llvm/include/llvm/TargetParser/X86TargetParser.def

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,11 +49,13 @@ X86_CPU_TYPE(ZHAOXIN_FAM7H, "zhaoxin_fam7h")
4949
X86_CPU_TYPE(INTEL_SIERRAFOREST, "sierraforest")
5050
X86_CPU_TYPE(INTEL_GRANDRIDGE, "grandridge")
5151
X86_CPU_TYPE(INTEL_CLEARWATERFOREST, "clearwaterforest")
52+
X86_CPU_TYPE(AMDFAM1AH, "amdfam1ah")
5253

5354
// Alternate names supported by __builtin_cpu_is and target multiversioning.
5455
X86_CPU_TYPE_ALIAS(INTEL_BONNELL, "atom")
5556
X86_CPU_TYPE_ALIAS(AMDFAM10H, "amdfam10")
5657
X86_CPU_TYPE_ALIAS(AMDFAM15H, "amdfam15")
58+
X86_CPU_TYPE_ALIAS(AMDFAM1AH, "amdfam1a")
5759
X86_CPU_TYPE_ALIAS(INTEL_SILVERMONT, "slm")
5860

5961
#undef X86_CPU_TYPE_ALIAS
@@ -104,6 +106,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_GRANITERAPIDS_D,"graniterapids-d")
104106
X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE, "arrowlake")
105107
X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE_S, "arrowlake-s")
106108
X86_CPU_SUBTYPE(INTEL_COREI7_PANTHERLAKE, "pantherlake")
109+
X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5, "znver5")
107110

108111
// Alternate names supported by __builtin_cpu_is and target multiversioning.
109112
X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "raptorlake")

‎llvm/include/llvm/TargetParser/X86TargetParser.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,7 @@ enum CPUKind {
142142
CK_ZNVER2,
143143
CK_ZNVER3,
144144
CK_ZNVER4,
145+
CK_ZNVER5,
145146
CK_x86_64,
146147
CK_x86_64_v2,
147148
CK_x86_64_v3,

‎llvm/lib/Target/X86/X86.td

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1549,6 +1549,19 @@ def ProcessorFeatures {
15491549
FeatureVPOPCNTDQ];
15501550
list<SubtargetFeature> ZN4Features =
15511551
!listconcat(ZN3Features, ZN4AdditionalFeatures);
1552+
1553+
1554+
list<SubtargetFeature> ZN5Tuning = ZN4Tuning;
1555+
list<SubtargetFeature> ZN5AdditionalFeatures = [FeatureVNNI,
1556+
FeatureMOVDIRI,
1557+
FeatureMOVDIR64B,
1558+
FeatureVP2INTERSECT,
1559+
FeaturePREFETCHI,
1560+
FeatureAVXVNNI
1561+
];
1562+
list<SubtargetFeature> ZN5Features =
1563+
!listconcat(ZN4Features, ZN5AdditionalFeatures);
1564+
15521565
}
15531566

15541567
//===----------------------------------------------------------------------===//
@@ -1898,6 +1911,8 @@ def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
18981911
ProcessorFeatures.ZN3Tuning>;
18991912
def : ProcModel<"znver4", Znver4Model, ProcessorFeatures.ZN4Features,
19001913
ProcessorFeatures.ZN4Tuning>;
1914+
def : ProcModel<"znver5", Znver4Model, ProcessorFeatures.ZN5Features,
1915+
ProcessorFeatures.ZN5Tuning>;
19011916

19021917
def : Proc<"geode", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],
19031918
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;

‎llvm/lib/Target/X86/X86PfmCounters.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -350,3 +350,4 @@ def ZnVer4PfmCounters : ProcPfmCounters {
350350
let ValidationCounters = DefaultAMDPfmValidationCounters;
351351
}
352352
def : PfmCountersBinding<"znver4", ZnVer4PfmCounters>;
353+
def : PfmCountersBinding<"znver5", ZnVer4PfmCounters>;

‎llvm/lib/TargetParser/Host.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1151,6 +1151,25 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
11511151
break; // "znver4"
11521152
}
11531153
break; // family 19h
1154+
case 26:
1155+
CPU = "znver5";
1156+
*Type = X86::AMDFAM1AH;
1157+
if (Model <= 0x77) {
1158+
// Models 00h-0Fh (Breithorn).
1159+
// Models 10h-1Fh (Breithorn-Dense).
1160+
// Models 20h-2Fh (Strix 1).
1161+
// Models 30h-37h (Strix 2).
1162+
// Models 38h-3Fh (Strix 3).
1163+
// Models 40h-4Fh (Granite Ridge).
1164+
// Models 50h-5Fh (Weisshorn).
1165+
// Models 60h-6Fh (Krackan1).
1166+
// Models 70h-77h (Sarlak).
1167+
CPU = "znver5";
1168+
*Subtype = X86::AMDFAM1AH_ZNVER5;
1169+
break; // "znver5"
1170+
}
1171+
break;
1172+
11541173
default:
11551174
break; // Unknown AMD CPU.
11561175
}

‎llvm/lib/TargetParser/X86TargetParser.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -238,6 +238,10 @@ static constexpr FeatureBitset FeaturesZNVER4 =
238238
FeatureAVX512BITALG | FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 |
239239
FeatureGFNI | FeatureSHSTK;
240240

241+
static constexpr FeatureBitset FeaturesZNVER5 =
242+
FeaturesZNVER4 | FeatureAVXVNNI | FeatureMOVDIRI | FeatureMOVDIR64B |
243+
FeatureAVX512VP2INTERSECT | FeaturePREFETCHI | FeatureAVXVNNI;
244+
241245
// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
242246
// X86TargetParser.def to here. They are assigned by following ways:
243247
// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
@@ -417,6 +421,7 @@ constexpr ProcInfo Processors[] = {
417421
{ {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2, '\0', false },
418422
{ {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false },
419423
{ {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
424+
{ {"znver5"}, CK_ZNVER5, FEATURE_AVX512VP2INTERSECT, FeaturesZNVER5, '\0', false },
420425
// Generic 64-bit processor.
421426
{ {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
422427
{ {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },

‎llvm/test/CodeGen/X86/bypass-slow-division-64.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
2424
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
2525
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
26+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
2627

2728
; Additional tests for 64-bit divide bypass
2829

‎llvm/test/CodeGen/X86/cmp16.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=X64,X64-FAST
1414
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=X64,X64-FAST
1515
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=X64,X64-FAST
16+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver5 | FileCheck %s --check-prefixes=X64,X64-FAST
1617

1718
define i1 @cmp16_reg_eq_reg(i16 %a0, i16 %a1) {
1819
; X86-GENERIC-LABEL: cmp16_reg_eq_reg:

‎llvm/test/CodeGen/X86/cpus-amd.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
3030
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
3131
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
32+
; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=znver5 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
3233

3334
define void @foo() {
3435
ret void

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