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[RISCV][SDAG] Fold select c, ~x, x into xor -c, x (#82462)
This patch lowers select of constants if `TrueV == ~FalseV`. Address the comment in #82456 (comment).
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2 files changed

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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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Original file line numberDiff line numberDiff line change
@@ -7239,6 +7239,16 @@ static SDValue combineSelectToBinOp(SDNode *N, SelectionDAG &DAG,
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}
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}
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// select c, ~x, x --> xor -c, x
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if (isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV)) {
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const APInt &TrueVal = TrueV->getAsAPIntVal();
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const APInt &FalseVal = FalseV->getAsAPIntVal();
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if (~TrueVal == FalseVal) {
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SDValue Neg = DAG.getNegative(CondV, DL, VT);
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return DAG.getNode(ISD::XOR, DL, VT, Neg, FalseV);
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}
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}
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// Try to fold (select (setcc lhs, rhs, cc), truev, falsev) into bitwise ops
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// when both truev and falsev are also setcc.
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if (CondV.getOpcode() == ISD::SETCC && TrueV.getOpcode() == ISD::SETCC &&

‎llvm/test/CodeGen/RISCV/select.ll

Lines changed: 177 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1449,3 +1449,180 @@ entry:
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%res = select i1 %cond, i32 %a, i32 %c
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ret i32 %res
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}
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define i32 @select_cst_not1(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: select_cst_not1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: slt a0, a0, a1
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; CHECK-NEXT: neg a0, a0
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; CHECK-NEXT: xori a0, a0, -6
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; CHECK-NEXT: ret
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%cond = icmp slt i32 %a, %b
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%ret = select i1 %cond, i32 5, i32 -6
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ret i32 %ret
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}
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define i32 @select_cst_not2(i32 signext %a) {
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; CHECK-LABEL: select_cst_not2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srai a0, a0, 31
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; CHECK-NEXT: xori a0, a0, -6
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; CHECK-NEXT: ret
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%cond = icmp slt i32 %a, 0
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%ret = select i1 %cond, i32 5, i32 -6
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ret i32 %ret
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}
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define i32 @select_cst_not3(i32 signext %a) {
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; CHECK-LABEL: select_cst_not3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srai a0, a0, 31
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; CHECK-NEXT: xori a0, a0, 5
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; CHECK-NEXT: ret
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%cond = icmp sgt i32 %a, -1
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%ret = select i1 %cond, i32 5, i32 -6
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ret i32 %ret
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}
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define i32 @select_cst_not4(i32 signext %a, i32 signext %b) {
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; RV32IM-LABEL: select_cst_not4:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: slt a0, a0, a1
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; RV32IM-NEXT: lui a1, 524288
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; RV32IM-NEXT: addi a1, a1, -1
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: select_cst_not4:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slt a0, a0, a1
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; RV64IM-NEXT: neg a0, a0
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; RV64IM-NEXT: lui a1, 524288
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; RV64IM-NEXT: addiw a1, a1, -1
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; RV64IM-NEXT: xor a0, a0, a1
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; RV64IM-NEXT: ret
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;
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; RV64IMXVTCONDOPS-LABEL: select_cst_not4:
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; RV64IMXVTCONDOPS: # %bb.0:
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; RV64IMXVTCONDOPS-NEXT: slt a0, a0, a1
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; RV64IMXVTCONDOPS-NEXT: neg a0, a0
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; RV64IMXVTCONDOPS-NEXT: lui a1, 524288
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; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -1
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; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1
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; RV64IMXVTCONDOPS-NEXT: ret
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;
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; RV32IMZICOND-LABEL: select_cst_not4:
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; RV32IMZICOND: # %bb.0:
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; RV32IMZICOND-NEXT: slt a0, a0, a1
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; RV32IMZICOND-NEXT: lui a1, 524288
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; RV32IMZICOND-NEXT: addi a1, a1, -1
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; RV32IMZICOND-NEXT: add a0, a0, a1
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; RV32IMZICOND-NEXT: ret
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;
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; RV64IMZICOND-LABEL: select_cst_not4:
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; RV64IMZICOND: # %bb.0:
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; RV64IMZICOND-NEXT: slt a0, a0, a1
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; RV64IMZICOND-NEXT: neg a0, a0
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; RV64IMZICOND-NEXT: lui a1, 524288
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; RV64IMZICOND-NEXT: addiw a1, a1, -1
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; RV64IMZICOND-NEXT: xor a0, a0, a1
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; RV64IMZICOND-NEXT: ret
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%cond = icmp slt i32 %a, %b
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%ret = select i1 %cond, i32 -2147483648, i32 2147483647
1532+
ret i32 %ret
1533+
}
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define i32 @select_cst_not5(i32 signext %a, i32 signext %b) {
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; RV32IM-LABEL: select_cst_not5:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: slt a0, a0, a1
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; RV32IM-NEXT: neg a0, a0
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; RV32IM-NEXT: lui a1, 16
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; RV32IM-NEXT: addi a1, a1, -5
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; RV32IM-NEXT: xor a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: select_cst_not5:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slt a0, a0, a1
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; RV64IM-NEXT: neg a0, a0
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; RV64IM-NEXT: lui a1, 16
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; RV64IM-NEXT: addiw a1, a1, -5
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; RV64IM-NEXT: xor a0, a0, a1
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; RV64IM-NEXT: ret
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;
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; RV64IMXVTCONDOPS-LABEL: select_cst_not5:
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; RV64IMXVTCONDOPS: # %bb.0:
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; RV64IMXVTCONDOPS-NEXT: slt a0, a0, a1
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; RV64IMXVTCONDOPS-NEXT: neg a0, a0
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; RV64IMXVTCONDOPS-NEXT: lui a1, 16
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; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -5
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; RV64IMXVTCONDOPS-NEXT: xor a0, a0, a1
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; RV64IMXVTCONDOPS-NEXT: ret
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;
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; RV32IMZICOND-LABEL: select_cst_not5:
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; RV32IMZICOND: # %bb.0:
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; RV32IMZICOND-NEXT: slt a0, a0, a1
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; RV32IMZICOND-NEXT: neg a0, a0
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; RV32IMZICOND-NEXT: lui a1, 16
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; RV32IMZICOND-NEXT: addi a1, a1, -5
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; RV32IMZICOND-NEXT: xor a0, a0, a1
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; RV32IMZICOND-NEXT: ret
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;
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; RV64IMZICOND-LABEL: select_cst_not5:
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; RV64IMZICOND: # %bb.0:
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; RV64IMZICOND-NEXT: slt a0, a0, a1
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; RV64IMZICOND-NEXT: neg a0, a0
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; RV64IMZICOND-NEXT: lui a1, 16
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; RV64IMZICOND-NEXT: addiw a1, a1, -5
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; RV64IMZICOND-NEXT: xor a0, a0, a1
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; RV64IMZICOND-NEXT: ret
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%cond = icmp slt i32 %a, %b
1581+
%ret = select i1 %cond, i32 -65532, i32 65531
1582+
ret i32 %ret
1583+
}
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define i32 @select_cst_unknown(i32 signext %a, i32 signext %b) {
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; RV32IM-LABEL: select_cst_unknown:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: mv a2, a0
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; RV32IM-NEXT: li a0, 5
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; RV32IM-NEXT: blt a2, a1, .LBB42_2
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; RV32IM-NEXT: # %bb.1:
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; RV32IM-NEXT: li a0, -7
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; RV32IM-NEXT: .LBB42_2:
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; RV32IM-NEXT: ret
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;
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; RV64IM-LABEL: select_cst_unknown:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: mv a2, a0
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; RV64IM-NEXT: li a0, 5
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; RV64IM-NEXT: blt a2, a1, .LBB42_2
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; RV64IM-NEXT: # %bb.1:
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; RV64IM-NEXT: li a0, -7
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; RV64IM-NEXT: .LBB42_2:
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; RV64IM-NEXT: ret
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;
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; RV64IMXVTCONDOPS-LABEL: select_cst_unknown:
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; RV64IMXVTCONDOPS: # %bb.0:
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; RV64IMXVTCONDOPS-NEXT: slt a0, a0, a1
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; RV64IMXVTCONDOPS-NEXT: li a1, -7
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; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
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; RV64IMXVTCONDOPS-NEXT: li a2, 5
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; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
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; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
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; RV64IMXVTCONDOPS-NEXT: ret
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;
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; CHECKZICOND-LABEL: select_cst_unknown:
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; CHECKZICOND: # %bb.0:
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; CHECKZICOND-NEXT: slt a0, a0, a1
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; CHECKZICOND-NEXT: li a1, -7
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; CHECKZICOND-NEXT: czero.nez a1, a1, a0
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; CHECKZICOND-NEXT: li a2, 5
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; CHECKZICOND-NEXT: czero.eqz a0, a2, a0
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; CHECKZICOND-NEXT: or a0, a0, a1
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; CHECKZICOND-NEXT: ret
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%cond = icmp slt i32 %a, %b
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%ret = select i1 %cond, i32 5, i32 -7
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ret i32 %ret
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}

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