@@ -10606,19 +10606,40 @@ SDValue SITargetLowering::LowerFDIV16(SDValue Op, SelectionDAG &DAG) const {
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return FastLowered;
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SDLoc SL(Op);
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- SDValue Src0 = Op.getOperand(0);
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- SDValue Src1 = Op.getOperand(1);
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-
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- SDValue CvtSrc0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
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- SDValue CvtSrc1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
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-
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- SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1);
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- SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1);
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-
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- SDValue FPRoundFlag = DAG.getTargetConstant(0, SL, MVT::i32);
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- SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);
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+ SDValue LHS = Op.getOperand(0);
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+ SDValue RHS = Op.getOperand(1);
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- return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0);
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+ // a32.u = opx(V_CVT_F32_F16, a.u);
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+ // b32.u = opx(V_CVT_F32_F16, b.u);
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+ // r32.u = opx(V_RCP_F32, b32.u);
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+ // q32.u = opx(V_MUL_F32, a32.u, r32.u);
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+ // e32.u = opx(V_MAD_F32, (b32.u^_neg32), q32.u, a32.u);
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+ // q32.u = opx(V_MAD_F32, e32.u, r32.u, q32.u);
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+ // e32.u = opx(V_MAD_F32, (b32.u^_neg32), q32.u, a32.u);
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+ // tmp.u = opx(V_MUL_F32, e32.u, r32.u);
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+ // tmp.u = opx(V_AND_B32, tmp.u, 0xff800000)
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+ // tmp.u = opx(V_FREXP_MANT_F32, tmp.u);
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+ // q32.u = opx(V_ADD_F32, tmp.u, q32.u);
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+ // q16.u = opx(V_CVT_F16_F32, q32.u);
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+ // q16.u = opx(V_DIV_FIXUP_F16, q16.u, b.u, a.u);
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+
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+ SDValue LHSExt = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, LHS);
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+ SDValue RHSExt = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, RHS);
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+ SDValue NegRHSExt = DAG.getNode(ISD::FNEG, SL, MVT::f32, RHSExt);
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+ SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, RHSExt);
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+ SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHSExt, Rcp);
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+ SDValue Err = DAG.getNode(ISD::FMA, SL, MVT::f32, NegRHSExt, Quot, LHSExt);
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+ Quot = DAG.getNode(ISD::FMA, SL, MVT::f32, Err, Rcp, Quot);
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+ Err = DAG.getNode(ISD::FMA, SL, MVT::f32, NegRHSExt, Quot, LHSExt);
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+ SDValue Tmp = DAG.getNode(ISD::FMUL, SL, MVT::f32, Err, Rcp);
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+ SDValue TmpCast = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Tmp);
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+ TmpCast = DAG.getNode(ISD::AND, SL, MVT::i32, TmpCast,
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+ DAG.getConstant(0xff800000, SL, MVT::i32));
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+ Tmp = DAG.getNode(ISD::BITCAST, SL, MVT::f32, TmpCast);
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+ Quot = DAG.getNode(ISD::FADD, SL, MVT::f32, Tmp, Quot);
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+ SDValue FPRoundFlag = DAG.getConstant(0, SL, MVT::i32);
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+ SDValue RDst = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);
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+ return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, RDst, RHS, LHS);
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}
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// Faster 2.5 ULP division that does not support denormals.
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