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[InstCombine] Set disjoint flag when turning Add into Or. (#72702)
The disjoint flag was recently added to IR in #72583
1 parent e666e27 commit 03d4a9d

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-340
lines changed

‎clang/test/CodeGen/aarch64-ls64-inline-asm.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -54,23 +54,23 @@ void store(const struct foo *input, void *addr)
5454
// CHECK-NEXT: [[S_SROA_10_0_INSERT_SHIFT:%.*]] = shl nuw i512 [[S_SROA_10_0_INSERT_EXT]], 448
5555
// CHECK-NEXT: [[S_SROA_9_0_INSERT_EXT:%.*]] = zext i64 [[CONV17]] to i512
5656
// CHECK-NEXT: [[S_SROA_9_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_9_0_INSERT_EXT]], 384
57-
// CHECK-NEXT: [[S_SROA_9_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_10_0_INSERT_SHIFT]], [[S_SROA_9_0_INSERT_SHIFT]]
57+
// CHECK-NEXT: [[S_SROA_9_0_INSERT_INSERT:%.*]] = or disjoint i512 [[S_SROA_10_0_INSERT_SHIFT]], [[S_SROA_9_0_INSERT_SHIFT]]
5858
// CHECK-NEXT: [[S_SROA_8_0_INSERT_EXT:%.*]] = zext i64 [[CONV14]] to i512
5959
// CHECK-NEXT: [[S_SROA_8_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_8_0_INSERT_EXT]], 320
60-
// CHECK-NEXT: [[S_SROA_8_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_9_0_INSERT_INSERT]], [[S_SROA_8_0_INSERT_SHIFT]]
60+
// CHECK-NEXT: [[S_SROA_8_0_INSERT_INSERT:%.*]] = or disjoint i512 [[S_SROA_9_0_INSERT_INSERT]], [[S_SROA_8_0_INSERT_SHIFT]]
6161
// CHECK-NEXT: [[S_SROA_7_0_INSERT_EXT:%.*]] = zext i64 [[CONV11]] to i512
6262
// CHECK-NEXT: [[S_SROA_7_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_7_0_INSERT_EXT]], 256
63-
// CHECK-NEXT: [[S_SROA_7_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_8_0_INSERT_INSERT]], [[S_SROA_7_0_INSERT_SHIFT]]
63+
// CHECK-NEXT: [[S_SROA_7_0_INSERT_INSERT:%.*]] = or disjoint i512 [[S_SROA_8_0_INSERT_INSERT]], [[S_SROA_7_0_INSERT_SHIFT]]
6464
// CHECK-NEXT: [[S_SROA_6_0_INSERT_EXT:%.*]] = zext i64 [[CONV8]] to i512
6565
// CHECK-NEXT: [[S_SROA_6_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_6_0_INSERT_EXT]], 192
66-
// CHECK-NEXT: [[S_SROA_6_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_7_0_INSERT_INSERT]], [[S_SROA_6_0_INSERT_SHIFT]]
66+
// CHECK-NEXT: [[S_SROA_6_0_INSERT_INSERT:%.*]] = or disjoint i512 [[S_SROA_7_0_INSERT_INSERT]], [[S_SROA_6_0_INSERT_SHIFT]]
6767
// CHECK-NEXT: [[S_SROA_5_0_INSERT_EXT:%.*]] = zext i64 [[CONV5]] to i512
6868
// CHECK-NEXT: [[S_SROA_5_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_5_0_INSERT_EXT]], 128
6969
// CHECK-NEXT: [[S_SROA_4_0_INSERT_EXT:%.*]] = zext i64 [[CONV2]] to i512
7070
// CHECK-NEXT: [[S_SROA_4_0_INSERT_SHIFT:%.*]] = shl nuw nsw i512 [[S_SROA_4_0_INSERT_EXT]], 64
71-
// CHECK-NEXT: [[S_SROA_4_0_INSERT_MASK:%.*]] = or i512 [[S_SROA_6_0_INSERT_INSERT]], [[S_SROA_5_0_INSERT_SHIFT]]
71+
// CHECK-NEXT: [[S_SROA_4_0_INSERT_MASK:%.*]] = or disjoint i512 [[S_SROA_6_0_INSERT_INSERT]], [[S_SROA_5_0_INSERT_SHIFT]]
7272
// CHECK-NEXT: [[S_SROA_0_0_INSERT_EXT:%.*]] = zext i64 [[CONV]] to i512
73-
// CHECK-NEXT: [[S_SROA_0_0_INSERT_MASK:%.*]] = or i512 [[S_SROA_4_0_INSERT_MASK]], [[S_SROA_4_0_INSERT_SHIFT]]
73+
// CHECK-NEXT: [[S_SROA_0_0_INSERT_MASK:%.*]] = or disjoint i512 [[S_SROA_4_0_INSERT_MASK]], [[S_SROA_4_0_INSERT_SHIFT]]
7474
// CHECK-NEXT: [[S_SROA_0_0_INSERT_INSERT:%.*]] = or i512 [[S_SROA_0_0_INSERT_MASK]], [[S_SROA_0_0_INSERT_EXT]]
7575
// CHECK-NEXT: tail call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 [[S_SROA_0_0_INSERT_INSERT]], ptr [[ADDR:%.*]]) #[[ATTR1]], !srcloc !8
7676
// CHECK-NEXT: ret void

‎clang/test/CodeGen/ms-intrinsics.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -444,7 +444,7 @@ unsigned char test_InterlockedCompareExchange128(
444444
// CHECK-64: [[EH:%[0-9]+]] = zext i64 %inc to i128
445445
// CHECK-64: [[EL:%[0-9]+]] = zext i64 %inc1 to i128
446446
// CHECK-64: [[EHS:%[0-9]+]] = shl nuw i128 [[EH]], 64
447-
// CHECK-64: [[EXP:%[0-9]+]] = or i128 [[EHS]], [[EL]]
447+
// CHECK-64: [[EXP:%[0-9]+]] = or disjoint i128 [[EHS]], [[EL]]
448448
// CHECK-64: [[ORG:%[0-9]+]] = load i128, ptr %incdec.ptr2, align 16
449449
// CHECK-64: [[RES:%[0-9]+]] = cmpxchg volatile ptr %incdec.ptr, i128 [[ORG]], i128 [[EXP]] seq_cst seq_cst, align 16
450450
// CHECK-64: [[OLD:%[0-9]+]] = extractvalue { i128, i1 } [[RES]], 0

‎llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1571,8 +1571,11 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
15711571

15721572
// A+B --> A|B iff A and B have no bits set in common.
15731573
WithCache<const Value *> LHSCache(LHS), RHSCache(RHS);
1574-
if (haveNoCommonBitsSet(LHSCache, RHSCache, SQ.getWithInstruction(&I)))
1575-
return BinaryOperator::CreateOr(LHS, RHS);
1574+
if (haveNoCommonBitsSet(LHSCache, RHSCache, SQ.getWithInstruction(&I))) {
1575+
auto *Or = BinaryOperator::CreateOr(LHS, RHS);
1576+
cast<PossiblyDisjointInst>(Or)->setIsDisjoint(true);
1577+
return Or;
1578+
}
15761579

15771580
if (Instruction *Ext = narrowMathIfNoOverflow(I))
15781581
return Ext;

‎llvm/test/Analysis/ValueTracking/assume.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ define i32 @assume_add(i32 %a, i32 %b) {
77
; CHECK-NEXT: [[LAST_TWO_DIGITS:%.*]] = and i32 [[T1]], 3
88
; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[LAST_TWO_DIGITS]], 0
99
; CHECK-NEXT: call void @llvm.assume(i1 [[T2]])
10-
; CHECK-NEXT: [[T3:%.*]] = or i32 [[T1]], 3
10+
; CHECK-NEXT: [[T3:%.*]] = or disjoint i32 [[T1]], 3
1111
; CHECK-NEXT: ret i32 [[T3]]
1212
;
1313
%t1 = add i32 %a, %b

‎llvm/test/Transforms/InstCombine/add.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,7 @@ define i32 @test8(i32 %A, i32 %B) {
199199
; CHECK-LABEL: @test8(
200200
; CHECK-NEXT: [[A1:%.*]] = and i32 [[A:%.*]], 7
201201
; CHECK-NEXT: [[B1:%.*]] = and i32 [[B:%.*]], 128
202-
; CHECK-NEXT: [[C:%.*]] = or i32 [[A1]], [[B1]]
202+
; CHECK-NEXT: [[C:%.*]] = or disjoint i32 [[A1]], [[B1]]
203203
; CHECK-NEXT: ret i32 [[C]]
204204
;
205205
%A1 = and i32 %A, 7
@@ -2565,7 +2565,7 @@ define i16 @add_sub_zext_constant(i8 %x) {
25652565
define <vscale x 1 x i32> @add_to_or_scalable(<vscale x 1 x i32> %in) {
25662566
; CHECK-LABEL: @add_to_or_scalable(
25672567
; CHECK-NEXT: [[SHL:%.*]] = shl <vscale x 1 x i32> [[IN:%.*]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
2568-
; CHECK-NEXT: [[ADD:%.*]] = or <vscale x 1 x i32> [[SHL]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
2568+
; CHECK-NEXT: [[ADD:%.*]] = or disjoint <vscale x 1 x i32> [[SHL]], shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
25692569
; CHECK-NEXT: ret <vscale x 1 x i32> [[ADD]]
25702570
;
25712571
%shl = shl <vscale x 1 x i32> %in, shufflevector (<vscale x 1 x i32> insertelement (<vscale x 1 x i32> poison, i32 1, i32 0), <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer)
@@ -2626,7 +2626,7 @@ define i5 @zext_sext_not(i4 %x) {
26262626
; CHECK-NEXT: [[ZX:%.*]] = zext i4 [[X:%.*]] to i5
26272627
; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1
26282628
; CHECK-NEXT: [[SNOTX:%.*]] = sext i4 [[NOTX]] to i5
2629-
; CHECK-NEXT: [[R:%.*]] = or i5 [[ZX]], [[SNOTX]]
2629+
; CHECK-NEXT: [[R:%.*]] = or disjoint i5 [[ZX]], [[SNOTX]]
26302630
; CHECK-NEXT: ret i5 [[R]]
26312631
;
26322632
%zx = zext i4 %x to i5
@@ -2643,7 +2643,7 @@ define i8 @zext_sext_not_commute(i4 %x) {
26432643
; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1
26442644
; CHECK-NEXT: [[SNOTX:%.*]] = sext i4 [[NOTX]] to i8
26452645
; CHECK-NEXT: call void @use(i8 [[SNOTX]])
2646-
; CHECK-NEXT: [[R:%.*]] = or i8 [[SNOTX]], [[ZX]]
2646+
; CHECK-NEXT: [[R:%.*]] = or disjoint i8 [[SNOTX]], [[ZX]]
26472647
; CHECK-NEXT: ret i8 [[R]]
26482648
;
26492649
%zx = zext i4 %x to i8
@@ -2660,7 +2660,7 @@ define i9 @sext_zext_not(i4 %x) {
26602660
; CHECK-NEXT: [[SX:%.*]] = sext i4 [[X:%.*]] to i9
26612661
; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1
26622662
; CHECK-NEXT: [[ZNOTX:%.*]] = zext i4 [[NOTX]] to i9
2663-
; CHECK-NEXT: [[R:%.*]] = or i9 [[SX]], [[ZNOTX]]
2663+
; CHECK-NEXT: [[R:%.*]] = or disjoint i9 [[SX]], [[ZNOTX]]
26642664
; CHECK-NEXT: ret i9 [[R]]
26652665
;
26662666
%sx = sext i4 %x to i9
@@ -2675,7 +2675,7 @@ define i9 @sext_zext_not_commute(i4 %x) {
26752675
; CHECK-NEXT: [[SX:%.*]] = sext i4 [[X:%.*]] to i9
26762676
; CHECK-NEXT: [[NOTX:%.*]] = xor i4 [[X]], -1
26772677
; CHECK-NEXT: [[ZNOTX:%.*]] = zext i4 [[NOTX]] to i9
2678-
; CHECK-NEXT: [[R:%.*]] = or i9 [[ZNOTX]], [[SX]]
2678+
; CHECK-NEXT: [[R:%.*]] = or disjoint i9 [[ZNOTX]], [[SX]]
26792679
; CHECK-NEXT: ret i9 [[R]]
26802680
;
26812681
%sx = sext i4 %x to i9

‎llvm/test/Transforms/InstCombine/add2.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ define i32 @test3(i32 %A) {
2828
; CHECK-LABEL: @test3(
2929
; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], 128
3030
; CHECK-NEXT: [[C:%.*]] = lshr i32 [[A]], 30
31-
; CHECK-NEXT: [[F:%.*]] = or i32 [[B]], [[C]]
31+
; CHECK-NEXT: [[F:%.*]] = or disjoint i32 [[B]], [[C]]
3232
; CHECK-NEXT: ret i32 [[F]]
3333
;
3434
%B = and i32 %A, 128
@@ -330,7 +330,7 @@ define i16 @mul_add_to_mul_9(i16 %a) {
330330
define i16 @add_cttz(i16 %a) {
331331
; CHECK-LABEL: @add_cttz(
332332
; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range [[RNG0:![0-9]+]]
333-
; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -8
333+
; CHECK-NEXT: [[B:%.*]] = or disjoint i16 [[CTTZ]], -8
334334
; CHECK-NEXT: ret i16 [[B]]
335335
;
336336
; llvm.cttz.i16(..., /*is_zero_undefined=*/true) implies the value returned
@@ -352,7 +352,7 @@ declare i16 @llvm.cttz.i16(i16, i1)
352352
define i16 @add_cttz_2(i16 %a) {
353353
; CHECK-LABEL: @add_cttz_2(
354354
; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range [[RNG1:![0-9]+]]
355-
; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -16
355+
; CHECK-NEXT: [[B:%.*]] = or disjoint i16 [[CTTZ]], -16
356356
; CHECK-NEXT: ret i16 [[B]]
357357
;
358358
; llvm.cttz.i16(..., /*is_zero_undefined=*/true) implies the value returned

‎llvm/test/Transforms/InstCombine/apint-add.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ define i128 @test8(i128 %x) {
149149
define i77 @test9(i77 %x) {
150150
; CHECK-LABEL: @test9(
151151
; CHECK-NEXT: [[TMP_2:%.*]] = and i77 [[X:%.*]], 562949953421310
152-
; CHECK-NEXT: [[TMP_4:%.*]] = or i77 [[TMP_2]], 1
152+
; CHECK-NEXT: [[TMP_4:%.*]] = or disjoint i77 [[TMP_2]], 1
153153
; CHECK-NEXT: ret i77 [[TMP_4]]
154154
;
155155
%tmp.2 = and i77 %x, 562949953421310

‎llvm/test/Transforms/InstCombine/apint-shift.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -481,7 +481,7 @@ define i44 @shl_lshr_eq_amt_multi_use(i44 %A) {
481481
; CHECK-LABEL: @shl_lshr_eq_amt_multi_use(
482482
; CHECK-NEXT: [[B:%.*]] = shl i44 [[A:%.*]], 33
483483
; CHECK-NEXT: [[C:%.*]] = and i44 [[A]], 2047
484-
; CHECK-NEXT: [[D:%.*]] = or i44 [[B]], [[C]]
484+
; CHECK-NEXT: [[D:%.*]] = or disjoint i44 [[B]], [[C]]
485485
; CHECK-NEXT: ret i44 [[D]]
486486
;
487487
%B = shl i44 %A, 33
@@ -496,7 +496,7 @@ define <2 x i44> @shl_lshr_eq_amt_multi_use_splat_vec(<2 x i44> %A) {
496496
; CHECK-LABEL: @shl_lshr_eq_amt_multi_use_splat_vec(
497497
; CHECK-NEXT: [[B:%.*]] = shl <2 x i44> [[A:%.*]], <i44 33, i44 33>
498498
; CHECK-NEXT: [[C:%.*]] = and <2 x i44> [[A]], <i44 2047, i44 2047>
499-
; CHECK-NEXT: [[D:%.*]] = or <2 x i44> [[B]], [[C]]
499+
; CHECK-NEXT: [[D:%.*]] = or disjoint <2 x i44> [[B]], [[C]]
500500
; CHECK-NEXT: ret <2 x i44> [[D]]
501501
;
502502
%B = shl <2 x i44> %A, <i44 33, i44 33>

‎llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ define i8 @add_bitreverse(i8 %a) {
4848
; CHECK-LABEL: @add_bitreverse(
4949
; CHECK-NEXT: [[B:%.*]] = and i8 [[A:%.*]], -4
5050
; CHECK-NEXT: [[REVERSE:%.*]] = call i8 @llvm.bitreverse.i8(i8 [[B]]), !range [[RNG0:![0-9]+]]
51-
; CHECK-NEXT: [[C:%.*]] = or i8 [[REVERSE]], -16
51+
; CHECK-NEXT: [[C:%.*]] = or disjoint i8 [[REVERSE]], -16
5252
; CHECK-NEXT: ret i8 [[C]]
5353
;
5454
%b = and i8 %a, 252

‎llvm/test/Transforms/InstCombine/masked-merge-add.ll

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ define i32 @p(i32 %x, i32 %y, i32 %m) {
2121
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
2222
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
2323
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
24-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
24+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
2525
; CHECK-NEXT: ret i32 [[RET]]
2626
;
2727
%and = and i32 %x, %m
@@ -36,7 +36,7 @@ define <2 x i32> @p_splatvec(<2 x i32> %x, <2 x i32> %y, <2 x i32> %m) {
3636
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]]
3737
; CHECK-NEXT: [[NEG:%.*]] = xor <2 x i32> [[M]], <i32 -1, i32 -1>
3838
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[NEG]], [[Y:%.*]]
39-
; CHECK-NEXT: [[RET:%.*]] = or <2 x i32> [[AND]], [[AND1]]
39+
; CHECK-NEXT: [[RET:%.*]] = or disjoint <2 x i32> [[AND]], [[AND1]]
4040
; CHECK-NEXT: ret <2 x i32> [[RET]]
4141
;
4242
%and = and <2 x i32> %x, %m
@@ -51,7 +51,7 @@ define <3 x i32> @p_vec_undef(<3 x i32> %x, <3 x i32> %y, <3 x i32> %m) {
5151
; CHECK-NEXT: [[AND:%.*]] = and <3 x i32> [[X:%.*]], [[M:%.*]]
5252
; CHECK-NEXT: [[NEG:%.*]] = xor <3 x i32> [[M]], <i32 -1, i32 undef, i32 -1>
5353
; CHECK-NEXT: [[AND1:%.*]] = and <3 x i32> [[NEG]], [[Y:%.*]]
54-
; CHECK-NEXT: [[RET:%.*]] = or <3 x i32> [[AND]], [[AND1]]
54+
; CHECK-NEXT: [[RET:%.*]] = or disjoint <3 x i32> [[AND]], [[AND1]]
5555
; CHECK-NEXT: ret <3 x i32> [[RET]]
5656
;
5757
%and = and <3 x i32> %x, %m
@@ -69,7 +69,7 @@ define i32 @p_constmask(i32 %x, i32 %y) {
6969
; CHECK-LABEL: @p_constmask(
7070
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 65280
7171
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], -65281
72-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
72+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
7373
; CHECK-NEXT: ret i32 [[RET]]
7474
;
7575
%and = and i32 %x, 65280
@@ -82,7 +82,7 @@ define <2 x i32> @p_constmask_splatvec(<2 x i32> %x, <2 x i32> %y) {
8282
; CHECK-LABEL: @p_constmask_splatvec(
8383
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 65280, i32 65280>
8484
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[Y:%.*]], <i32 -65281, i32 -65281>
85-
; CHECK-NEXT: [[RET:%.*]] = or <2 x i32> [[AND]], [[AND1]]
85+
; CHECK-NEXT: [[RET:%.*]] = or disjoint <2 x i32> [[AND]], [[AND1]]
8686
; CHECK-NEXT: ret <2 x i32> [[RET]]
8787
;
8888
%and = and <2 x i32> %x, <i32 65280, i32 65280>
@@ -125,7 +125,7 @@ define i32 @p_constmask2(i32 %x, i32 %y) {
125125
; CHECK-LABEL: @p_constmask2(
126126
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 61440
127127
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], -65281
128-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
128+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
129129
; CHECK-NEXT: ret i32 [[RET]]
130130
;
131131
%and = and i32 %x, 61440
@@ -138,7 +138,7 @@ define <2 x i32> @p_constmask2_splatvec(<2 x i32> %x, <2 x i32> %y) {
138138
; CHECK-LABEL: @p_constmask2_splatvec(
139139
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 61440, i32 61440>
140140
; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[Y:%.*]], <i32 -65281, i32 -65281>
141-
; CHECK-NEXT: [[RET:%.*]] = or <2 x i32> [[AND]], [[AND1]]
141+
; CHECK-NEXT: [[RET:%.*]] = or disjoint <2 x i32> [[AND]], [[AND1]]
142142
; CHECK-NEXT: ret <2 x i32> [[RET]]
143143
;
144144
%and = and <2 x i32> %x, <i32 61440, i32 61440>
@@ -185,7 +185,7 @@ define i32 @p_commutative0(i32 %x, i32 %y, i32 %m) {
185185
; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]]
186186
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
187187
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
188-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
188+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
189189
; CHECK-NEXT: ret i32 [[RET]]
190190
;
191191
%and = and i32 %m, %x ; swapped order
@@ -201,7 +201,7 @@ define i32 @p_commutative1(i32 %x, i32 %m) {
201201
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
202202
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
203203
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y]], [[NEG]]
204-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
204+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
205205
; CHECK-NEXT: ret i32 [[RET]]
206206
;
207207
%y = call i32 @gen32()
@@ -217,7 +217,7 @@ define i32 @p_commutative2(i32 %x, i32 %y, i32 %m) {
217217
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
218218
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
219219
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
220-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
220+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
221221
; CHECK-NEXT: ret i32 [[RET]]
222222
;
223223
%and = and i32 %x, %m
@@ -233,7 +233,7 @@ define i32 @p_commutative3(i32 %x, i32 %m) {
233233
; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]]
234234
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
235235
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y]], [[NEG]]
236-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
236+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
237237
; CHECK-NEXT: ret i32 [[RET]]
238238
;
239239
%y = call i32 @gen32()
@@ -249,7 +249,7 @@ define i32 @p_commutative4(i32 %x, i32 %y, i32 %m) {
249249
; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]]
250250
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
251251
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
252-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
252+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
253253
; CHECK-NEXT: ret i32 [[RET]]
254254
;
255255
%and = and i32 %m, %x ; swapped order
@@ -265,7 +265,7 @@ define i32 @p_commutative5(i32 %x, i32 %m) {
265265
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
266266
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
267267
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y]], [[NEG]]
268-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
268+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
269269
; CHECK-NEXT: ret i32 [[RET]]
270270
;
271271
%y = call i32 @gen32()
@@ -282,7 +282,7 @@ define i32 @p_commutative6(i32 %x, i32 %m) {
282282
; CHECK-NEXT: [[AND:%.*]] = and i32 [[M:%.*]], [[X:%.*]]
283283
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
284284
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y]], [[NEG]]
285-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
285+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
286286
; CHECK-NEXT: ret i32 [[RET]]
287287
;
288288
%y = call i32 @gen32()
@@ -297,7 +297,7 @@ define i32 @p_constmask_commutative(i32 %x, i32 %y) {
297297
; CHECK-LABEL: @p_constmask_commutative(
298298
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 65280
299299
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], -65281
300-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND1]], [[AND]]
300+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND1]], [[AND]]
301301
; CHECK-NEXT: ret i32 [[RET]]
302302
;
303303
%and = and i32 %x, 65280
@@ -319,7 +319,7 @@ define i32 @n0_oneuse(i32 %x, i32 %y, i32 %m) {
319319
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
320320
; CHECK-NEXT: [[NEG:%.*]] = xor i32 [[M]], -1
321321
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
322-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
322+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
323323
; CHECK-NEXT: call void @use32(i32 [[AND]])
324324
; CHECK-NEXT: call void @use32(i32 [[NEG]])
325325
; CHECK-NEXT: call void @use32(i32 [[AND1]])
@@ -339,7 +339,7 @@ define i32 @n0_constmask_oneuse(i32 %x, i32 %y) {
339339
; CHECK-LABEL: @n0_constmask_oneuse(
340340
; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 65280
341341
; CHECK-NEXT: [[AND1:%.*]] = and i32 [[Y:%.*]], -65281
342-
; CHECK-NEXT: [[RET:%.*]] = or i32 [[AND]], [[AND1]]
342+
; CHECK-NEXT: [[RET:%.*]] = or disjoint i32 [[AND]], [[AND1]]
343343
; CHECK-NEXT: call void @use32(i32 [[AND]])
344344
; CHECK-NEXT: call void @use32(i32 [[AND1]])
345345
; CHECK-NEXT: ret i32 [[RET]]

‎llvm/test/Transforms/InstCombine/minmax-intrinsics.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1934,7 +1934,7 @@ define i8 @smax_offset_uses(i8 %x) {
19341934
define <3 x i8> @smin_offset(<3 x i8> %x) {
19351935
; CHECK-LABEL: @smin_offset(
19361936
; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i8> @llvm.smin.v3i8(<3 x i8> [[X:%.*]], <3 x i8> <i8 -127, i8 -127, i8 -127>)
1937-
; CHECK-NEXT: [[M:%.*]] = or <3 x i8> [[TMP1]], <i8 124, i8 124, i8 124>
1937+
; CHECK-NEXT: [[M:%.*]] = or disjoint <3 x i8> [[TMP1]], <i8 124, i8 124, i8 124>
19381938
; CHECK-NEXT: ret <3 x i8> [[M]]
19391939
;
19401940
%a = add nsw nuw <3 x i8> %x, <i8 124, i8 124, i8 124>

‎llvm/test/Transforms/InstCombine/or.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1476,7 +1476,7 @@ define i32 @mul_no_common_bits(i32 %p1, i32 %p2) {
14761476
; CHECK-LABEL: @mul_no_common_bits(
14771477
; CHECK-NEXT: [[X:%.*]] = and i32 [[P1:%.*]], 7
14781478
; CHECK-NEXT: [[Y:%.*]] = shl i32 [[P2:%.*]], 3
1479-
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[Y]], 1
1479+
; CHECK-NEXT: [[TMP1:%.*]] = or disjoint i32 [[Y]], 1
14801480
; CHECK-NEXT: [[R:%.*]] = mul i32 [[X]], [[TMP1]]
14811481
; CHECK-NEXT: ret i32 [[R]]
14821482
;

‎llvm/test/Transforms/InstCombine/pr72433.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ define i32 @widget(i32 %arg, i32 %arg1) {
99
; CHECK-NEXT: [[TMP0:%.*]] = zext i1 [[ICMP]] to i32
1010
; CHECK-NEXT: [[MUL:%.*]] = shl nuw nsw i32 20, [[TMP0]]
1111
; CHECK-NEXT: [[XOR:%.*]] = zext i1 [[ICMP]] to i32
12-
; CHECK-NEXT: [[ADD9:%.*]] = or i32 [[MUL]], [[XOR]]
12+
; CHECK-NEXT: [[ADD9:%.*]] = or disjoint i32 [[MUL]], [[XOR]]
1313
; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[ICMP]] to i32
1414
; CHECK-NEXT: [[MUL2:%.*]] = shl nuw nsw i32 [[ADD9]], [[TMP1]]
1515
; CHECK-NEXT: ret i32 [[MUL2]]

‎llvm/test/Transforms/InstCombine/ptrtoint-nullgep.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -602,7 +602,7 @@ define i64 @fold_ptrtoint_nested_array_two_vars_plus_const(i64 %x, i64 %y) {
602602
; INSTCOMBINE-NEXT: [[PTR_IDX:%.*]] = shl i64 [[X]], 3
603603
; INSTCOMBINE-NEXT: [[PTR_IDX1:%.*]] = shl i64 [[Y]], 2
604604
; INSTCOMBINE-NEXT: [[PTR_OFFS:%.*]] = add i64 [[PTR_IDX]], [[PTR_IDX1]]
605-
; INSTCOMBINE-NEXT: [[PTR_OFFS2:%.*]] = or i64 [[PTR_OFFS]], 2
605+
; INSTCOMBINE-NEXT: [[PTR_OFFS2:%.*]] = or disjoint i64 [[PTR_OFFS]], 2
606606
; INSTCOMBINE-NEXT: ret i64 [[PTR_OFFS2]]
607607
;
608608
%ptr = getelementptr [2 x [2 x i16]], ptr addrspace(1) null, i64 %x, i64 %y, i64 1

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