[RISCV] Add Hazard3 CPU

Luke Wren's Hazard3 is an open-source 32-bit RISC-V core. The core's
source code and docs are available on github:
https://github.com/wren6991/hazard3

The core has just hit 1.0 today, which seems to me to be a good time to
add it as a named CPU in LLVM.

Author: lenary

clang/test/Driver/riscv-cpus.c

@@ -402,6 +402,23 @@
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt"
 // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s
+// MCPU-HAZARD3: "-target-cpu" "hazard3"
+// MCPU-HAZARD3-SAME: "-target-feature" "+m"
+// MCPU-HAZARD3-SAME: "-target-feature" "+a"
+// MCPU-HAZARD3-SAME: "-target-feature" "+c"
+// MCPU-HAZARD3-SAME: "-target-feature" "+b"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zicsr"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zifencei"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zcb"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zcmp"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zba"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zbb"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zbc"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zbkb"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zbs"
+// MCPU-HAZARD3-SAME: "-target-abi" "ilp32"
+
 // Check failed cases
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s

llvm/docs/ReleaseNotes.rst

@@ -108,6 +108,7 @@ Changes to the RISC-V Backend
   fill value) rather than NOPs.
 * Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64``
 * ``-mcpu=sifive-p470`` was added.
+* Added Hazard3 CPU: ``-mcpu=hazard3`` (32-bit only).
 * Fixed length vector support using RVV instructions now requires VLEN>=64. This
   means Zve32x and Zve32f will also require Zvl64b. The prior support was
   largely untested.

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -454,3 +454,21 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
                                         FeatureStdExtZvkt,
                                         FeatureStdExtZvl256b]),
                                        [TuneDLenFactor2]>;
+
+def HAZARD3 : RISCVProcessorModel<"hazard3",
+                                  NoSchedModel,
+                                  [Feature32Bit,
+                                   FeatureStdExtI,
+                                   FeatureStdExtM,
+                                   FeatureStdExtA,
+                                   FeatureStdExtB,
+                                   FeatureStdExtC,
+                                   FeatureStdExtZicsr,
+                                   FeatureStdExtZifencei,
+                                   FeatureStdExtZba,
+                                   FeatureStdExtZbb,
+                                   FeatureStdExtZbc,
+                                   FeatureStdExtZbs,
+                                   FeatureStdExtZbkb,
+                                   FeatureStdExtZcb,
+                                   FeatureStdExtZcmp]>;