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‎llvm/test/CodeGen/AArch64/ctlo.ll

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s --mtriple=aarch64 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s --mtriple=aarch64 -global-isel -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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declare i8 @llvm.ctlz.i8(i8, i1)
6+
declare i16 @llvm.ctlz.i16(i16, i1)
7+
declare i32 @llvm.ctlz.i32(i32, i1)
8+
declare i64 @llvm.ctlz.i64(i64, i1)
9+
10+
define i8 @ctlo_i8(i8 %x) {
11+
; CHECK-LABEL: ctlo_i8:
12+
; CHECK: // %bb.0:
13+
; CHECK-NEXT: mov w8, #255 // =0xff
14+
; CHECK-NEXT: bic w8, w8, w0
15+
; CHECK-NEXT: clz w8, w8
16+
; CHECK-NEXT: sub w0, w8, #24
17+
; CHECK-NEXT: ret
18+
%tmp1 = xor i8 %x, -1
19+
%tmp2 = call i8 @llvm.ctlz.i8( i8 %tmp1, i1 false )
20+
ret i8 %tmp2
21+
}
22+
23+
define i8 @ctlo_i8_undef(i8 %x) {
24+
; CHECK-SD-LABEL: ctlo_i8_undef:
25+
; CHECK-SD: // %bb.0:
26+
; CHECK-SD-NEXT: mvn w8, w0
27+
; CHECK-SD-NEXT: lsl w8, w8, #24
28+
; CHECK-SD-NEXT: clz w0, w8
29+
; CHECK-SD-NEXT: ret
30+
;
31+
; CHECK-GI-LABEL: ctlo_i8_undef:
32+
; CHECK-GI: // %bb.0:
33+
; CHECK-GI-NEXT: mov w8, #255 // =0xff
34+
; CHECK-GI-NEXT: bic w8, w8, w0
35+
; CHECK-GI-NEXT: clz w8, w8
36+
; CHECK-GI-NEXT: sub w0, w8, #24
37+
; CHECK-GI-NEXT: ret
38+
%tmp1 = xor i8 %x, -1
39+
%tmp2 = call i8 @llvm.ctlz.i8( i8 %tmp1, i1 true )
40+
ret i8 %tmp2
41+
}
42+
43+
define i16 @ctlo_i16(i16 %x) {
44+
; CHECK-LABEL: ctlo_i16:
45+
; CHECK: // %bb.0:
46+
; CHECK-NEXT: mov w8, #65535 // =0xffff
47+
; CHECK-NEXT: bic w8, w8, w0
48+
; CHECK-NEXT: clz w8, w8
49+
; CHECK-NEXT: sub w0, w8, #16
50+
; CHECK-NEXT: ret
51+
%tmp1 = xor i16 %x, -1
52+
%tmp2 = call i16 @llvm.ctlz.i16( i16 %tmp1, i1 false )
53+
ret i16 %tmp2
54+
}
55+
56+
define i16 @ctlo_i16_undef(i16 %x) {
57+
; CHECK-SD-LABEL: ctlo_i16_undef:
58+
; CHECK-SD: // %bb.0:
59+
; CHECK-SD-NEXT: mvn w8, w0
60+
; CHECK-SD-NEXT: lsl w8, w8, #16
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; CHECK-SD-NEXT: clz w0, w8
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; CHECK-SD-NEXT: ret
63+
;
64+
; CHECK-GI-LABEL: ctlo_i16_undef:
65+
; CHECK-GI: // %bb.0:
66+
; CHECK-GI-NEXT: mov w8, #65535 // =0xffff
67+
; CHECK-GI-NEXT: bic w8, w8, w0
68+
; CHECK-GI-NEXT: clz w8, w8
69+
; CHECK-GI-NEXT: sub w0, w8, #16
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; CHECK-GI-NEXT: ret
71+
%tmp1 = xor i16 %x, -1
72+
%tmp2 = call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true )
73+
ret i16 %tmp2
74+
}
75+
76+
define i32 @ctlo_i32(i32 %x) {
77+
; CHECK-LABEL: ctlo_i32:
78+
; CHECK: // %bb.0:
79+
; CHECK-NEXT: mvn w8, w0
80+
; CHECK-NEXT: clz w0, w8
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; CHECK-NEXT: ret
82+
%tmp1 = xor i32 %x, -1
83+
%tmp2 = call i32 @llvm.ctlz.i32( i32 %tmp1, i1 false )
84+
ret i32 %tmp2
85+
}
86+
87+
define i32 @ctlo_i32_undef(i32 %x) {
88+
; CHECK-LABEL: ctlo_i32_undef:
89+
; CHECK: // %bb.0:
90+
; CHECK-NEXT: mvn w8, w0
91+
; CHECK-NEXT: clz w0, w8
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; CHECK-NEXT: ret
93+
%tmp1 = xor i32 %x, -1
94+
%tmp2 = call i32 @llvm.ctlz.i32( i32 %tmp1, i1 true )
95+
ret i32 %tmp2
96+
}
97+
98+
define i64 @ctlo_i64(i64 %x) {
99+
; CHECK-LABEL: ctlo_i64:
100+
; CHECK: // %bb.0:
101+
; CHECK-NEXT: mvn x8, x0
102+
; CHECK-NEXT: clz x0, x8
103+
; CHECK-NEXT: ret
104+
%tmp1 = xor i64 %x, -1
105+
%tmp2 = call i64 @llvm.ctlz.i64( i64 %tmp1, i1 false )
106+
ret i64 %tmp2
107+
}
108+
109+
define i64 @ctlo_i64_undef(i64 %x) {
110+
; CHECK-LABEL: ctlo_i64_undef:
111+
; CHECK: // %bb.0:
112+
; CHECK-NEXT: mvn x8, x0
113+
; CHECK-NEXT: clz x0, x8
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; CHECK-NEXT: ret
115+
%tmp1 = xor i64 %x, -1
116+
%tmp2 = call i64 @llvm.ctlz.i64( i64 %tmp1, i1 true )
117+
ret i64 %tmp2
118+
}

‎llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll

Lines changed: 165 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2624,6 +2624,171 @@ define <vscale x 1 x i9> @vp_ctlz_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
26242624
%v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
26252625
ret <vscale x 1 x i9> %v
26262626
}
2627+
define <vscale x 1 x i9> @vp_ctlo_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2628+
; CHECK-LABEL: vp_ctlo_nxv1i9:
2629+
; CHECK: # %bb.0:
2630+
; CHECK-NEXT: li a1, 511
2631+
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2632+
; CHECK-NEXT: vxor.vx v8, v8, a1
2633+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2634+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
2635+
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2636+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2637+
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2638+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2639+
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2640+
; CHECK-NEXT: li a0, 142
2641+
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2642+
; CHECK-NEXT: li a0, 16
2643+
; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
2644+
; CHECK-NEXT: li a0, 7
2645+
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
2646+
; CHECK-NEXT: ret
2647+
;
2648+
; CHECK-ZVBB-LABEL: vp_ctlo_nxv1i9:
2649+
; CHECK-ZVBB: # %bb.0:
2650+
; CHECK-ZVBB-NEXT: li a1, 511
2651+
; CHECK-ZVBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2652+
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1
2653+
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2654+
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
2655+
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2656+
; CHECK-ZVBB-NEXT: li a0, 7
2657+
; CHECK-ZVBB-NEXT: vsub.vx v8, v8, a0, v0.t
2658+
; CHECK-ZVBB-NEXT: ret
2659+
%va.not = xor <vscale x 1 x i9> %va, splat (i9 -1)
2660+
%v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va.not, i1 false, <vscale x 1 x i1> %m, i32 %evl)
2661+
ret <vscale x 1 x i9> %v
2662+
}
2663+
define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2664+
; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9:
2665+
; CHECK: # %bb.0:
2666+
; CHECK-NEXT: li a1, 511
2667+
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2668+
; CHECK-NEXT: vxor.vx v8, v8, a1
2669+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2670+
; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
2671+
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2672+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2673+
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2674+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2675+
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2676+
; CHECK-NEXT: li a0, 142
2677+
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2678+
; CHECK-NEXT: ret
2679+
;
2680+
; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9:
2681+
; CHECK-ZVBB: # %bb.0:
2682+
; CHECK-ZVBB-NEXT: li a1, 511
2683+
; CHECK-ZVBB-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2684+
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1
2685+
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2686+
; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
2687+
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2688+
; CHECK-ZVBB-NEXT: ret
2689+
%va.not = xor <vscale x 1 x i9> %va, splat (i9 -1)
2690+
%v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va.not, i1 true, <vscale x 1 x i1> %m, i32 %evl)
2691+
ret <vscale x 1 x i9> %v
2692+
}
2693+
2694+
define <vscale x 1 x i9> @vp_ctlo_nxv1i9_vp_xor(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2695+
; CHECK-LABEL: vp_ctlo_nxv1i9_vp_xor:
2696+
; CHECK: # %bb.0:
2697+
; CHECK-NEXT: li a1, 511
2698+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2699+
; CHECK-NEXT: vxor.vx v8, v8, a1, v0.t
2700+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
2701+
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2702+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2703+
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2704+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2705+
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2706+
; CHECK-NEXT: li a0, 142
2707+
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2708+
; CHECK-NEXT: li a0, 16
2709+
; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
2710+
; CHECK-NEXT: li a0, 7
2711+
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
2712+
; CHECK-NEXT: ret
2713+
;
2714+
; CHECK-ZVBB-LABEL: vp_ctlo_nxv1i9_vp_xor:
2715+
; CHECK-ZVBB: # %bb.0:
2716+
; CHECK-ZVBB-NEXT: li a1, 511
2717+
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2718+
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1, v0.t
2719+
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
2720+
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2721+
; CHECK-ZVBB-NEXT: li a0, 7
2722+
; CHECK-ZVBB-NEXT: vsub.vx v8, v8, a0, v0.t
2723+
; CHECK-ZVBB-NEXT: ret
2724+
%va.not = call <vscale x 1 x i9> @llvm.vp.xor.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i9> splat (i9 -1), <vscale x 1 x i1> %m, i32 %evl)
2725+
%v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va.not, i1 false, <vscale x 1 x i1> %m, i32 %evl)
2726+
ret <vscale x 1 x i9> %v
2727+
}
2728+
2729+
define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9_vp_xor(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2730+
; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9_vp_xor:
2731+
; CHECK: # %bb.0:
2732+
; CHECK-NEXT: li a1, 511
2733+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2734+
; CHECK-NEXT: vxor.vx v8, v8, a1, v0.t
2735+
; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
2736+
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2737+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2738+
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2739+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2740+
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2741+
; CHECK-NEXT: li a0, 142
2742+
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2743+
; CHECK-NEXT: ret
2744+
;
2745+
; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9_vp_xor:
2746+
; CHECK-ZVBB: # %bb.0:
2747+
; CHECK-ZVBB-NEXT: li a1, 511
2748+
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2749+
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1, v0.t
2750+
; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
2751+
; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2752+
; CHECK-ZVBB-NEXT: ret
2753+
%va.not = call <vscale x 1 x i9> @llvm.vp.xor.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i9> splat (i9 -1), <vscale x 1 x i1> %m, i32 %evl)
2754+
%v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va.not, i1 true, <vscale x 1 x i1> %m, i32 %evl)
2755+
ret <vscale x 1 x i9> %v
2756+
}
2757+
2758+
define <vscale x 1 x i9> @vp_ctlo_zero_nxv1i9_unpredicated_ctlz_with_vp_xor(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2759+
; CHECK-LABEL: vp_ctlo_zero_nxv1i9_unpredicated_ctlz_with_vp_xor:
2760+
; CHECK: # %bb.0:
2761+
; CHECK-NEXT: li a1, 511
2762+
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2763+
; CHECK-NEXT: vxor.vx v8, v8, a1, v0.t
2764+
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2765+
; CHECK-NEXT: vand.vx v8, v8, a1
2766+
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
2767+
; CHECK-NEXT: vnsrl.wi v8, v9, 23
2768+
; CHECK-NEXT: li a0, 142
2769+
; CHECK-NEXT: vrsub.vx v8, v8, a0
2770+
; CHECK-NEXT: li a0, 16
2771+
; CHECK-NEXT: vminu.vx v8, v8, a0
2772+
; CHECK-NEXT: li a0, 7
2773+
; CHECK-NEXT: vsub.vx v8, v8, a0
2774+
; CHECK-NEXT: ret
2775+
;
2776+
; CHECK-ZVBB-LABEL: vp_ctlo_zero_nxv1i9_unpredicated_ctlz_with_vp_xor:
2777+
; CHECK-ZVBB: # %bb.0:
2778+
; CHECK-ZVBB-NEXT: li a1, 511
2779+
; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2780+
; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1, v0.t
2781+
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2782+
; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
2783+
; CHECK-ZVBB-NEXT: vclz.v v8, v8
2784+
; CHECK-ZVBB-NEXT: li a0, 7
2785+
; CHECK-ZVBB-NEXT: vsub.vx v8, v8, a0
2786+
; CHECK-ZVBB-NEXT: ret
2787+
%va.not = call <vscale x 1 x i9> @llvm.vp.xor.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i9> splat (i9 -1), <vscale x 1 x i1> %m, i32 %evl)
2788+
%v = call <vscale x 1 x i9> @llvm.ctlz(<vscale x 1 x i9> %va.not, i1 false)
2789+
ret <vscale x 1 x i9> %v
2790+
}
2791+
26272792
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
26282793
; RV32: {{.*}}
26292794
; RV64: {{.*}}

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