Update nvgpu-to-nvvm.mlir

grypp · web-flow · commit 0500d070b313 · 2025-03-27T09:29:03.000+01:00
diff --git a/mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir b/mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
@@ -803,7 +803,7 @@ func.func @tma_prefetch(%tensorMap1d: !tensorMap1d, %p : i1) {
 }
 
 
-// CHECK-LABEL: @tma_prefetch(
+// CHECK-LABEL: @tma_fence(
 // CHECK-SAME: %[[arg0:[a-zA-Z0-9_]+]]: !nvgpu.tensormap.descriptor<tensor = memref<128xf32, 3>, swizzle = none, l2promo = none, oob = nan, interleave = none>, %[[arg1:[a-zA-Z0-9_]+]]: i1
 func.func @tma_fence(%tensorMap1d: !tensorMap1d) {
   // CHECK: %[[S0:.+]] = builtin.unrealized_conversion_cast %[[arg0]] : !nvgpu.tensormap.descriptor<tensor = memref<128xf32, 3>, swizzle = none, l2promo = none, oob = nan, interleave = none> to !llvm.ptr

Original file line number	Diff line number	Diff line change
`@@ -803,7 +803,7 @@ func.func @tma_prefetch(%tensorMap1d: !tensorMap1d, %p : i1) {`
`803`	`803`	`}`
`804`	`804`
`805`	`805`
`806`		`-// CHECK-LABEL: @tma_prefetch(`
	`806`	`+// CHECK-LABEL: @tma_fence(`
`807`	`807`	`// CHECK-SAME: %[[arg0:[a-zA-Z0-9_]+]]: !nvgpu.tensormap.descriptor<tensor = memref<128xf32, 3>, swizzle = none, l2promo = none, oob = nan, interleave = none>, %[[arg1:[a-zA-Z0-9_]+]]: i1`
`808`	`808`	`func.func @tma_fence(%tensorMap1d: !tensorMap1d) {`
`809`	`809`	`// CHECK: %[[S0:.+]] = builtin.unrealized_conversion_cast %[[arg0]] : !nvgpu.tensormap.descriptor<tensor = memref<128xf32, 3>, swizzle = none, l2promo = none, oob = nan, interleave = none> to !llvm.ptr`