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adam-yangadam-yang
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Added WaveActiveMax
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12 files changed

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12 files changed

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‎clang/include/clang/Basic/Builtins.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4795,6 +4795,12 @@ def HLSLWaveActiveCountBits : LangBuiltin<"HLSL_LANG"> {
47954795
let Prototype = "unsigned int(bool)";
47964796
}
47974797

4798+
def HLSLWaveActiveMax : LangBuiltin<"HLSL_LANG"> {
4799+
let Spellings = ["__builtin_hlsl_wave_active_max"];
4800+
let Attributes = [NoThrow, Const];
4801+
let Prototype = "void (...)";
4802+
}
4803+
47984804
def HLSLWaveActiveSum : LangBuiltin<"HLSL_LANG"> {
47994805
let Spellings = ["__builtin_hlsl_wave_active_sum"];
48004806
let Attributes = [NoThrow, Const];

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19098,6 +19098,25 @@ static Intrinsic::ID getWaveActiveSumIntrinsic(llvm::Triple::ArchType Arch,
1909819098
}
1909919099
}
1910019100

19101+
// Return wave active sum that corresponds to the QT scalar type
19102+
static Intrinsic::ID getWaveActiveMaxIntrinsic(llvm::Triple::ArchType Arch,
19103+
CGHLSLRuntime &RT, QualType QT) {
19104+
switch (Arch) {
19105+
case llvm::Triple::spirv:
19106+
if (QT->isUnsignedIntegerType())
19107+
return llvm::Intrinsic::spv_wave_reduce_umax;
19108+
return llvm::Intrinsic::spv_wave_reduce_max;
19109+
case llvm::Triple::dxil: {
19110+
if (QT->isUnsignedIntegerType())
19111+
return llvm::Intrinsic::dx_wave_reduce_umax;
19112+
return llvm::Intrinsic::dx_wave_reduce_max;
19113+
}
19114+
default:
19115+
llvm_unreachable("Intrinsic WaveActiveMax"
19116+
" not supported by target architecture");
19117+
}
19118+
}
19119+
1910119120
Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
1910219121
const CallExpr *E,
1910319122
ReturnValueSlot ReturnValue) {
@@ -19427,6 +19446,23 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
1942719446
/*AssumeConvergent=*/true),
1942819447
ArrayRef{OpExpr}, "hlsl.wave.active.sum");
1942919448
}
19449+
case Builtin::BI__builtin_hlsl_wave_active_max: {
19450+
// Due to the use of variadic arguments, explicitly retreive argument
19451+
Value *OpExpr = EmitScalarExpr(E->getArg(0));
19452+
llvm::FunctionType *FT = llvm::FunctionType::get(
19453+
OpExpr->getType(), ArrayRef{OpExpr->getType()}, false);
19454+
Intrinsic::ID IID = getWaveActiveMaxIntrinsic(
19455+
getTarget().getTriple().getArch(), CGM.getHLSLRuntime(),
19456+
E->getArg(0)->getType());
19457+
19458+
// Get overloaded name
19459+
std::string Name =
19460+
Intrinsic::getName(IID, ArrayRef{OpExpr->getType()}, &CGM.getModule());
19461+
return EmitRuntimeCall(CGM.CreateRuntimeFunction(FT, Name, {},
19462+
/*Local=*/false,
19463+
/*AssumeConvergent=*/true),
19464+
ArrayRef{OpExpr}, "hlsl.wave.active.max");
19465+
}
1943019466
case Builtin::BI__builtin_hlsl_wave_get_lane_index: {
1943119467
// We don't define a SPIR-V intrinsic, instead it is a SPIR-V built-in
1943219468
// defined in SPIRVBuiltins.td. So instead we manually get the matching name

‎clang/lib/Sema/SemaHLSL.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2422,6 +2422,7 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
24222422
TheCall->setType(ArgTyA);
24232423
break;
24242424
}
2425+
case Builtin::BI__builtin_hlsl_wave_active_max:
24252426
case Builtin::BI__builtin_hlsl_wave_active_sum: {
24262427
if (SemaRef.checkArgCount(TheCall, 1))
24272428
return true;

‎clang/test/CodeGenHLSL/builtins/WaveActiveMax.hlsl

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \
2+
// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \
3+
// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
4+
// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \
5+
// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \
6+
// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV
7+
8+
// Test basic lowering to runtime function call.
9+
10+
// CHECK-LABEL: test_int
11+
int test_int(int expr) {
12+
// CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.max.i32([[TY]] %[[#]])
13+
// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.reduce.max.i32([[TY]] %[[#]])
14+
// CHECK: ret [[TY]] %[[RET]]
15+
return WaveActiveMax(expr);
16+
}
17+
18+
// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.reduce.max.i32([[TY]]) #[[#attr:]]
19+
// CHECK-SPIRV: declare spir_func [[TY]] @llvm.spv.wave.reduce.max.i32([[TY]]) #[[#attr:]]
20+
21+
// CHECK-LABEL: test_uint64_t
22+
uint64_t test_uint64_t(uint64_t expr) {
23+
// CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.umax.i64([[TY]] %[[#]])
24+
// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.reduce.umax.i64([[TY]] %[[#]])
25+
// CHECK: ret [[TY]] %[[RET]]
26+
return WaveActiveMax(expr);
27+
}
28+
29+
// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.reduce.umax.i64([[TY]]) #[[#attr:]]
30+
// CHECK-SPIRV: declare spir_func [[TY]] @llvm.spv.wave.reduce.umax.i64([[TY]]) #[[#attr:]]
31+
32+
// Test basic lowering to runtime function call with array and float value.
33+
34+
// CHECK-LABEL: test_floatv4
35+
float4 test_floatv4(float4 expr) {
36+
// CHECK-SPIRV: %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn spir_func [[TY1:.*]] @llvm.spv.wave.reduce.max.v4f32([[TY1]] %[[#]]
37+
// CHECK-DXIL: %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn [[TY1:.*]] @llvm.dx.wave.reduce.max.v4f32([[TY1]] %[[#]])
38+
// CHECK: ret [[TY1]] %[[RET1]]
39+
return WaveActiveMax(expr);
40+
}
41+
42+
// CHECK-DXIL: declare [[TY1]] @llvm.dx.wave.reduce.max.v4f32([[TY1]]) #[[#attr]]
43+
// CHECK-SPIRV: declare spir_func [[TY1]] @llvm.spv.wave.reduce.max.v4f32([[TY1]]) #[[#attr]]
44+
45+
// CHECK: attributes #[[#attr]] = {{{.*}} convergent {{.*}}}
46+

‎clang/test/SemaHLSL/BuiltIns/WaveActiveMax-errors.hlsl

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify
2+
3+
int test_too_few_arg() {
4+
return __builtin_hlsl_wave_active_max();
5+
// expected-error@-1 {{too few arguments to function call, expected 1, have 0}}
6+
}
7+
8+
float2 test_too_many_arg(float2 p0) {
9+
return __builtin_hlsl_wave_active_max(p0, p0);
10+
// expected-error@-1 {{too many arguments to function call, expected 1, have 2}}
11+
}
12+
13+
bool test_expr_bool_type_check(bool p0) {
14+
return __builtin_hlsl_wave_active_max(p0);
15+
// expected-error@-1 {{invalid operand of type 'bool'}}
16+
}
17+
18+
bool2 test_expr_bool_vec_type_check(bool2 p0) {
19+
return __builtin_hlsl_wave_active_max(p0);
20+
// expected-error@-1 {{invalid operand of type 'bool2' (aka 'vector<bool, 2>')}}
21+
}
22+
23+
struct S { float f; };
24+
25+
S test_expr_struct_type_check(S p0) {
26+
return __builtin_hlsl_wave_active_max(p0);
27+
// expected-error@-1 {{invalid operand of type 'S' where a scalar or vector is required}}
28+
}
29+

‎llvm/include/llvm/IR/IntrinsicsDirectX.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -105,6 +105,8 @@ def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1
105105
def int_dx_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
106106
def int_dx_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
107107
def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent, IntrNoMem]>;
108+
def int_dx_wave_reduce_max : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
109+
def int_dx_wave_reduce_umax : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
108110
def int_dx_wave_reduce_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
109111
def int_dx_wave_reduce_usum : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
110112
def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;

‎llvm/include/llvm/IR/IntrinsicsSPIRV.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,8 @@ let TargetPrefix = "spv" in {
9191
def int_spv_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
9292
def int_spv_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
9393
def int_spv_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>;
94+
def int_spv_wave_reduce_umax : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
95+
def int_spv_wave_reduce_max : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
9496
def int_spv_wave_reduce_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>;
9597
def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
9698
def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>;

‎llvm/lib/Target/DirectX/DXIL.td

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1000,6 +1000,16 @@ def WaveActiveOp : DXILOp<119, waveActiveOp> {
10001000
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Sum>,
10011001
IntrinArgI8<SignedOpKind_Unsigned>
10021002
]>,
1003+
IntrinSelect<int_dx_wave_reduce_max,
1004+
[
1005+
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Max>,
1006+
IntrinArgI8<SignedOpKind_Signed>
1007+
]>,
1008+
IntrinSelect<int_dx_wave_reduce_umax,
1009+
[
1010+
IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Max>,
1011+
IntrinArgI8<SignedOpKind_Unsigned>
1012+
]>,
10031013
];
10041014

10051015
let arguments = [OverloadTy, Int8Ty, Int8Ty];

‎llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,8 @@ bool DirectXTTIImpl::isTargetIntrinsicTriviallyScalarizable(
4040
switch (ID) {
4141
case Intrinsic::dx_frac:
4242
case Intrinsic::dx_rsqrt:
43+
case Intrinsic::dx_wave_reduce_max:
44+
case Intrinsic::dx_wave_reduce_umax:
4345
case Intrinsic::dx_wave_reduce_sum:
4446
case Intrinsic::dx_wave_reduce_usum:
4547
case Intrinsic::dx_wave_readlane:

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,9 @@ class SPIRVInstructionSelector : public InstructionSelector {
215215
bool selectDot4AddPackedExpansion(Register ResVReg, const SPIRVType *ResType,
216216
MachineInstr &I) const;
217217

218+
bool selectWaveReduceMax(Register ResVReg, const SPIRVType *ResType,
219+
MachineInstr &I, bool IsUnsigned) const;
220+
218221
bool selectWaveReduceSum(Register ResVReg, const SPIRVType *ResType,
219222
MachineInstr &I) const;
220223

@@ -2132,6 +2135,32 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits(
21322135
return Result;
21332136
}
21342137

2138+
bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg,
2139+
const SPIRVType *ResType,
2140+
MachineInstr &I, bool IsUnsigned) const {
2141+
assert(I.getNumOperands() == 3);
2142+
assert(I.getOperand(2).isReg());
2143+
MachineBasicBlock &BB = *I.getParent();
2144+
Register InputRegister = I.getOperand(2).getReg();
2145+
SPIRVType *InputType = GR.getSPIRVTypeForVReg(InputRegister);
2146+
2147+
if (!InputType)
2148+
report_fatal_error("Input Type could not be determined.");
2149+
2150+
SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII);
2151+
// Retreive the operation to use based on input type
2152+
bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat);
2153+
auto IntegerOpcodeType = IsUnsigned ? SPIRV::OpGroupNonUniformUMax : SPIRV::OpGroupNonUniformSMax;
2154+
auto Opcode =
2155+
IsFloatTy ? SPIRV::OpGroupNonUniformFMax : IntegerOpcodeType;
2156+
return BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode))
2157+
.addDef(ResVReg)
2158+
.addUse(GR.getSPIRVTypeID(ResType))
2159+
.addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII))
2160+
.addImm(SPIRV::GroupOperation::Reduce)
2161+
.addUse(I.getOperand(2).getReg());
2162+
}
2163+
21352164
bool SPIRVInstructionSelector::selectWaveReduceSum(Register ResVReg,
21362165
const SPIRVType *ResType,
21372166
MachineInstr &I) const {
@@ -3086,6 +3115,10 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
30863115
return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny);
30873116
case Intrinsic::spv_wave_is_first_lane:
30883117
return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect);
3118+
case Intrinsic::spv_wave_reduce_umax:
3119+
return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/true);
3120+
case Intrinsic::spv_wave_reduce_max:
3121+
return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/false);
30893122
case Intrinsic::spv_wave_reduce_sum:
30903123
return selectWaveReduceSum(ResVReg, ResType, I);
30913124
case Intrinsic::spv_wave_readlane:

‎llvm/test/CodeGen/DirectX/WaveActiveMax.ll

Lines changed: 143 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,143 @@
1+
; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library < %s | FileCheck %s
2+
3+
; Test that for scalar values, WaveActiveMax maps down to the DirectX op
4+
5+
define noundef half @wave_active_max_half(half noundef %expr) {
6+
entry:
7+
; CHECK: call half @dx.op.waveActiveOp.f16(i32 119, half %expr, i8 3, i8 0)
8+
%ret = call half @llvm.dx.wave.reduce.max.f16(half %expr)
9+
ret half %ret
10+
}
11+
12+
define noundef float @wave_active_max_float(float noundef %expr) {
13+
entry:
14+
; CHECK: call float @dx.op.waveActiveOp.f32(i32 119, float %expr, i8 3, i8 0)
15+
%ret = call float @llvm.dx.wave.reduce.max.f32(float %expr)
16+
ret float %ret
17+
}
18+
19+
define noundef double @wave_active_max_double(double noundef %expr) {
20+
entry:
21+
; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr, i8 3, i8 0)
22+
%ret = call double @llvm.dx.wave.reduce.max.f64(double %expr)
23+
ret double %ret
24+
}
25+
26+
define noundef i16 @wave_active_max_i16(i16 noundef %expr) {
27+
entry:
28+
; CHECK: call i16 @dx.op.waveActiveOp.i16(i32 119, i16 %expr, i8 3, i8 0)
29+
%ret = call i16 @llvm.dx.wave.reduce.max.i16(i16 %expr)
30+
ret i16 %ret
31+
}
32+
33+
define noundef i32 @wave_active_max_i32(i32 noundef %expr) {
34+
entry:
35+
; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr, i8 3, i8 0)
36+
%ret = call i32 @llvm.dx.wave.reduce.max.i32(i32 %expr)
37+
ret i32 %ret
38+
}
39+
40+
define noundef i64 @wave_active_max_i64(i64 noundef %expr) {
41+
entry:
42+
; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr, i8 3, i8 0)
43+
%ret = call i64 @llvm.dx.wave.reduce.max.i64(i64 %expr)
44+
ret i64 %ret
45+
}
46+
47+
define noundef i16 @wave_active_umax_i16(i16 noundef %expr) {
48+
entry:
49+
; CHECK: call i16 @dx.op.waveActiveOp.i16(i32 119, i16 %expr, i8 3, i8 1)
50+
%ret = call i16 @llvm.dx.wave.reduce.umax.i16(i16 %expr)
51+
ret i16 %ret
52+
}
53+
54+
define noundef i32 @wave_active_umax_i32(i32 noundef %expr) {
55+
entry:
56+
; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr, i8 3, i8 1)
57+
%ret = call i32 @llvm.dx.wave.reduce.umax.i32(i32 %expr)
58+
ret i32 %ret
59+
}
60+
61+
define noundef i64 @wave_active_umax_i64(i64 noundef %expr) {
62+
entry:
63+
; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr, i8 3, i8 1)
64+
%ret = call i64 @llvm.dx.wave.reduce.umax.i64(i64 %expr)
65+
ret i64 %ret
66+
}
67+
68+
declare half @llvm.dx.wave.reduce.max.f16(half)
69+
declare float @llvm.dx.wave.reduce.max.f32(float)
70+
declare double @llvm.dx.wave.reduce.max.f64(double)
71+
72+
declare i16 @llvm.dx.wave.reduce.max.i16(i16)
73+
declare i32 @llvm.dx.wave.reduce.max.i32(i32)
74+
declare i64 @llvm.dx.wave.reduce.max.i64(i64)
75+
76+
declare i16 @llvm.dx.wave.reduce.umax.i16(i16)
77+
declare i32 @llvm.dx.wave.reduce.umax.i32(i32)
78+
declare i64 @llvm.dx.wave.reduce.umax.i64(i64)
79+
80+
; Test that for vector values, WaveActiveMax scalarizes and maps down to the
81+
; DirectX op
82+
83+
define noundef <2 x half> @wave_active_max_v2half(<2 x half> noundef %expr) {
84+
entry:
85+
; CHECK: call half @dx.op.waveActiveOp.f16(i32 119, half %expr.i0, i8 3, i8 0)
86+
; CHECK: call half @dx.op.waveActiveOp.f16(i32 119, half %expr.i1, i8 3, i8 0)
87+
%ret = call <2 x half> @llvm.dx.wave.reduce.max.v2f16(<2 x half> %expr)
88+
ret <2 x half> %ret
89+
}
90+
91+
define noundef <3 x i32> @wave_active_max_v3i32(<3 x i32> noundef %expr) {
92+
entry:
93+
; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i0, i8 3, i8 0)
94+
; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i1, i8 3, i8 0)
95+
; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i2, i8 3, i8 0)
96+
%ret = call <3 x i32> @llvm.dx.wave.reduce.max.v3i32(<3 x i32> %expr)
97+
ret <3 x i32> %ret
98+
}
99+
100+
define noundef <4 x double> @wave_active_max_v4f64(<4 x double> noundef %expr) {
101+
entry:
102+
; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr.i0, i8 3, i8 0)
103+
; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr.i1, i8 3, i8 0)
104+
; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr.i2, i8 3, i8 0)
105+
; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr.i3, i8 3, i8 0)
106+
%ret = call <4 x double> @llvm.dx.wave.reduce.max.v4f64(<4 x double> %expr)
107+
ret <4 x double> %ret
108+
}
109+
110+
declare <2 x half> @llvm.dx.wave.reduce.max.v2f16(<2 x half>)
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declare <3 x i32> @llvm.dx.wave.reduce.max.v3i32(<3 x i32>)
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declare <4 x double> @llvm.dx.wave.reduce.max.v4f64(<4 x double>)
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define noundef <2 x i16> @wave_active_umax_v2i16(<2 x i16> noundef %expr) {
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entry:
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; CHECK: call i16 @dx.op.waveActiveOp.i16(i32 119, i16 %expr.i0, i8 3, i8 1)
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; CHECK: call i16 @dx.op.waveActiveOp.i16(i32 119, i16 %expr.i1, i8 3, i8 1)
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%ret = call <2 x i16> @llvm.dx.wave.reduce.umax.v2f16(<2 x i16> %expr)
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ret <2 x i16> %ret
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}
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define noundef <3 x i32> @wave_active_umax_v3i32(<3 x i32> noundef %expr) {
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entry:
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; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i0, i8 3, i8 1)
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; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i1, i8 3, i8 1)
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; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i2, i8 3, i8 1)
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%ret = call <3 x i32> @llvm.dx.wave.reduce.umax.v3i32(<3 x i32> %expr)
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ret <3 x i32> %ret
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}
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define noundef <4 x i64> @wave_active_umax_v4f64(<4 x i64> noundef %expr) {
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entry:
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; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr.i0, i8 3, i8 1)
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; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr.i1, i8 3, i8 1)
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; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr.i2, i8 3, i8 1)
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; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr.i3, i8 3, i8 1)
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%ret = call <4 x i64> @llvm.dx.wave.reduce.umax.v4f64(<4 x i64> %expr)
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ret <4 x i64> %ret
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}
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declare <2 x i16> @llvm.dx.wave.reduce.umax.v2f16(<2 x i16>)
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declare <3 x i32> @llvm.dx.wave.reduce.umax.v3i32(<3 x i32>)
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declare <4 x i64> @llvm.dx.wave.reduce.umax.v4f64(<4 x i64>)

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