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michaelmaitlandmichaelmaitland
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[RISCV][GISEL] Instruction select for scalable G_SELECT
SelectionDAG has SELECT and VSELECT SELECT restricts the condition operand to an i1 and the true and false operands can be vectors. The result of a SELECT has the same type as the true and false operands. VSELECT has a vector condition operand and the true and false operands must be vectors. The result of a VSELECT has a vector result. GlobalISel has G_SELECT which has condition operand that is an i1 if the true and false operands are scalar and a vector type with i1 elements if the true and false operands are vector. A G_SELECT acts like a ISD::SELECT when the operands are all scalar, and an ISD::VSELECT when the operands are are scalar. A G_SELECT cannot act like a ISD::SELECT with an i1 condition and vector operands because the type system. In this patch, we would like to take advantage of the patterns written for SELECT and VSELECT, so we mark G_SELECT equivalent to both SELECT and VSELECT to reuse the patterns. Since we cannot write a `G_SELECT (s1), (vector-ty), (vector-ty)`, we don't have to worry about accidently matching the SDAG patterns of that nature. We will probably need a way to represent an i1 condition with vector true and false operands in the future. That can be the topic of another patch.
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‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

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@@ -90,6 +90,7 @@ def : GINodeEquiv<G_UDIVFIX, udivfix>;
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def : GINodeEquiv<G_SDIVFIXSAT, sdivfixsat>;
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def : GINodeEquiv<G_UDIVFIXSAT, udivfixsat>;
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def : GINodeEquiv<G_SELECT, select>;
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def : GINodeEquiv<G_SELECT, vselect>;
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def : GINodeEquiv<G_FNEG, fneg>;
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def : GINodeEquiv<G_FPEXT, fpextend>;
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def : GINodeEquiv<G_FPTRUNC, fpround>;

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/select.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s
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# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s
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---
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name: select_nxv1i8
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legalized: true
8+
regBankSelected: true
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tracksRegLiveness: true
10+
body: |
11+
bb.0.entry:
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; RV32I-LABEL: name: select_nxv1i8
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; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
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; RV32I-NEXT: $v0 = COPY [[DEF]]
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; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
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; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
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; RV32I-NEXT: PseudoRET implicit $v8
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;
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; RV64I-LABEL: name: select_nxv1i8
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; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
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; RV64I-NEXT: $v0 = COPY [[DEF]]
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; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
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; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
28+
; RV64I-NEXT: PseudoRET implicit $v8
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%0:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF
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%1:vrb(<vscale x 2 x s8>) = G_IMPLICIT_DEF
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%2:vrb(<vscale x 2 x s8>) = G_SELECT %0(<vscale x 2 x s1>), %1, %1
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$v8 = COPY %2(<vscale x 2 x s8>)
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PseudoRET implicit $v8
34+
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...
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---
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name: select_nxv4i8
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
42+
bb.0.entry:
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; RV32I-LABEL: name: select_nxv4i8
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; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
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; RV32I-NEXT: $v0 = COPY [[DEF]]
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; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
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; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
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; RV32I-NEXT: PseudoRET implicit $v8
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;
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; RV64I-LABEL: name: select_nxv4i8
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; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
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; RV64I-NEXT: $v0 = COPY [[DEF]]
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; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
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; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
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; RV64I-NEXT: PseudoRET implicit $v8
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%0:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF
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%1:vrb(<vscale x 8 x s8>) = G_IMPLICIT_DEF
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%2:vrb(<vscale x 8 x s8>) = G_SELECT %0(<vscale x 8 x s1>), %1, %1
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$v8 = COPY %2(<vscale x 8 x s8>)
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PseudoRET implicit $v8
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...
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---
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name: select_nxv16i8
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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; RV32I-LABEL: name: select_nxv16i8
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; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
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; RV32I-NEXT: $v0 = COPY [[DEF]]
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; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
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; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
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; RV32I-NEXT: PseudoRET implicit $v8m4
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;
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; RV64I-LABEL: name: select_nxv16i8
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; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
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; RV64I-NEXT: $v0 = COPY [[DEF]]
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; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 3 /* e8 */
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; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
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; RV64I-NEXT: PseudoRET implicit $v8m4
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%0:vrb(<vscale x 32 x s1>) = G_IMPLICIT_DEF
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%1:vrb(<vscale x 32 x s8>) = G_IMPLICIT_DEF
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%2:vrb(<vscale x 32 x s8>) = G_SELECT %0(<vscale x 32 x s1>), %1, %1
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$v8m4 = COPY %2(<vscale x 32 x s8>)
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PseudoRET implicit $v8m4
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...
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---
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name: select_nxv64i8
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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; RV32I-LABEL: name: select_nxv64i8
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; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
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; RV32I-NEXT: $v0 = COPY [[DEF]]
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; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
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; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
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; RV32I-NEXT: PseudoRET implicit $v8
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;
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; RV64I-LABEL: name: select_nxv64i8
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; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
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; RV64I-NEXT: $v0 = COPY [[DEF]]
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; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
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; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]
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; RV64I-NEXT: PseudoRET implicit $v8
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%0:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF
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%1:vrb(<vscale x 1 x s16>) = G_IMPLICIT_DEF
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%2:vrb(<vscale x 1 x s16>) = G_SELECT %0(<vscale x 1 x s1>), %1, %1
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$v8 = COPY %2(<vscale x 1 x s16>)
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PseudoRET implicit $v8
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...
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---
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name: select_nxv2i16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
135+
bb.0.entry:
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; RV32I-LABEL: name: select_nxv2i16
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; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
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; RV32I-NEXT: $v0 = COPY [[DEF]]
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; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
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; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
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; RV32I-NEXT: PseudoRET implicit $v8
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;
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; RV64I-LABEL: name: select_nxv2i16
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; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
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; RV64I-NEXT: $v0 = COPY [[DEF]]
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; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
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; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]
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; RV64I-NEXT: PseudoRET implicit $v8
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%0:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF
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%1:vrb(<vscale x 4 x s16>) = G_IMPLICIT_DEF
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%2:vrb(<vscale x 4 x s16>) = G_SELECT %0(<vscale x 4 x s1>), %1, %1
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$v8 = COPY %2(<vscale x 4 x s16>)
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PseudoRET implicit $v8
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...
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---
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name: select_nxv8i16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
166+
bb.0.entry:
167+
; RV32I-LABEL: name: select_nxv8i16
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; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
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; RV32I-NEXT: $v0 = COPY [[DEF]]
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; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
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; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
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; RV32I-NEXT: PseudoRET implicit $v8m4
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;
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; RV64I-LABEL: name: select_nxv8i16
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; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF
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; RV64I-NEXT: $v0 = COPY [[DEF]]
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; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 4 /* e16 */
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; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]
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; RV64I-NEXT: PseudoRET implicit $v8m4
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%0:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF
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%1:vrb(<vscale x 16 x s16>) = G_IMPLICIT_DEF
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%2:vrb(<vscale x 16 x s16>) = G_SELECT %0(<vscale x 16 x s1>), %1, %1
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$v8m4 = COPY %2(<vscale x 16 x s16>)
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PseudoRET implicit $v8m4
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190+
...
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---
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name: select_nxv32i16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
196+
body: |
197+
bb.0.entry:
198+
; RV32I-LABEL: name: select_nxv32i16
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; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
202+
; RV32I-NEXT: $v0 = COPY [[DEF]]
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; RV32I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
204+
; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]]
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; RV32I-NEXT: PseudoRET implicit $v8
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;
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; RV64I-LABEL: name: select_nxv32i16
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; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
210+
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
211+
; RV64I-NEXT: $v0 = COPY [[DEF]]
212+
; RV64I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
213+
; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]]
214+
; RV64I-NEXT: PseudoRET implicit $v8
215+
%0:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF
216+
%1:vrb(<vscale x 1 x s32>) = G_IMPLICIT_DEF
217+
%2:vrb(<vscale x 1 x s32>) = G_SELECT %0(<vscale x 1 x s1>), %1, %1
218+
$v8 = COPY %2(<vscale x 1 x s32>)
219+
PseudoRET implicit $v8
220+
221+
...
222+
---
223+
name: select_nxv2i32
224+
legalized: true
225+
regBankSelected: true
226+
tracksRegLiveness: true
227+
body: |
228+
bb.0.entry:
229+
; RV32I-LABEL: name: select_nxv2i32
230+
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
231+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
232+
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
233+
; RV32I-NEXT: $v0 = COPY [[DEF]]
234+
; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
235+
; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
236+
; RV32I-NEXT: PseudoRET implicit $v8m2
237+
;
238+
; RV64I-LABEL: name: select_nxv2i32
239+
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
240+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
241+
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
242+
; RV64I-NEXT: $v0 = COPY [[DEF]]
243+
; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
244+
; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
245+
; RV64I-NEXT: PseudoRET implicit $v8m2
246+
%0:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF
247+
%1:vrb(<vscale x 4 x s32>) = G_IMPLICIT_DEF
248+
%2:vrb(<vscale x 4 x s32>) = G_SELECT %0(<vscale x 4 x s1>), %1, %1
249+
$v8m2 = COPY %2(<vscale x 4 x s32>)
250+
PseudoRET implicit $v8m2
251+
252+
...
253+
---
254+
name: select_nxv8i32
255+
legalized: true
256+
regBankSelected: true
257+
tracksRegLiveness: true
258+
body: |
259+
bb.0.entry:
260+
; RV32I-LABEL: name: select_nxv8i32
261+
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
262+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
263+
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
264+
; RV32I-NEXT: $v0 = COPY [[DEF]]
265+
; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
266+
; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
267+
; RV32I-NEXT: PseudoRET implicit $v8m8
268+
;
269+
; RV64I-LABEL: name: select_nxv8i32
270+
; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
271+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
272+
; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
273+
; RV64I-NEXT: $v0 = COPY [[DEF]]
274+
; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 5 /* e32 */
275+
; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
276+
; RV64I-NEXT: PseudoRET implicit $v8m8
277+
%0:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF
278+
%1:vrb(<vscale x 16 x s32>) = G_IMPLICIT_DEF
279+
%2:vrb(<vscale x 16 x s32>) = G_SELECT %0(<vscale x 16 x s1>), %1, %1
280+
$v8m8 = COPY %2(<vscale x 16 x s32>)
281+
PseudoRET implicit $v8m8
282+
283+
...
284+
---
285+
name: select_nxv1i64
286+
legalized: true
287+
regBankSelected: true
288+
tracksRegLiveness: true
289+
body: |
290+
bb.0.entry:
291+
; RV32I-LABEL: name: select_nxv1i64
292+
; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
293+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
294+
; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
295+
; RV32I-NEXT: $v0 = COPY [[DEF]]
296+
; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */
297+
; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
298+
; RV32I-NEXT: PseudoRET implicit $v8m2
299+
;
300+
; RV64I-LABEL: name: select_nxv1i64
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; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF
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; RV64I-NEXT: $v0 = COPY [[DEF]]
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; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */
306+
; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]
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; RV64I-NEXT: PseudoRET implicit $v8m2
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%0:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF
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%1:vrb(<vscale x 2 x s64>) = G_IMPLICIT_DEF
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%2:vrb(<vscale x 2 x s64>) = G_SELECT %0(<vscale x 2 x s1>), %1, %1
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$v8m2 = COPY %2(<vscale x 2 x s64>)
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PseudoRET implicit $v8m2
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...
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---
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name: select_nxv4i64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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; RV32I-LABEL: name: select_nxv4i64
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; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
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; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
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; RV32I-NEXT: $v0 = COPY [[DEF]]
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; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */
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; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
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; RV32I-NEXT: PseudoRET implicit $v8m8
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;
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; RV64I-LABEL: name: select_nxv4i64
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; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF
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; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF
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; RV64I-NEXT: $v0 = COPY [[DEF]]
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; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], $v0, -1, 6 /* e64 */
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; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]
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; RV64I-NEXT: PseudoRET implicit $v8m8
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%0:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF
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%1:vrb(<vscale x 8 x s64>) = G_IMPLICIT_DEF
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%2:vrb(<vscale x 8 x s64>) = G_SELECT %0(<vscale x 8 x s1>), %1, %1
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$v8m8 = COPY %2(<vscale x 8 x s64>)
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PseudoRET implicit $v8m8
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...

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