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jurahuljurahul
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[TableGen] Emit OpName as an enum class instead of a namespace
- Change InstrInfoEmitter to emit OpName as an enum class instead of an anonymous enum in the OpName namespace. - This will help clearly distinguish between vales that are OpNames vs just operand indices and should help avoid bugs due to confusion between the two. - Also updated AMDGPU, RISCV, and WebAssembly backends to conform to the new definition of OpName (mostly mechanical changes).
1 parent f50efe9 commit 05ad717

21 files changed

+181
-183
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1777,7 +1777,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17771777
bool validateMIMGDim(const MCInst &Inst, const OperandVector &Operands);
17781778
bool validateMIMGMSAA(const MCInst &Inst);
17791779
bool validateOpSel(const MCInst &Inst);
1780-
bool validateNeg(const MCInst &Inst, int OpName);
1780+
bool validateNeg(const MCInst &Inst, AMDGPU::OpName OpName);
17811781
bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
17821782
bool validateVccOperand(MCRegister Reg) const;
17831783
bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
@@ -3953,8 +3953,9 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
39533953
const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
39543954
AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
39553955
int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
3956-
int RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc
3957-
: AMDGPU::OpName::rsrc;
3956+
AMDGPU::OpName RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG)
3957+
? AMDGPU::OpName::srsrc
3958+
: AMDGPU::OpName::rsrc;
39583959
int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RSrcOpName);
39593960
int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
39603961
int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);
@@ -4651,7 +4652,7 @@ bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
46514652
return true;
46524653
}
46534654

4654-
bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) {
4655+
bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, AMDGPU::OpName OpName) {
46554656
assert(OpName == AMDGPU::OpName::neg_lo || OpName == AMDGPU::OpName::neg_hi);
46564657

46574658
const unsigned Opc = Inst.getOpcode();
@@ -4676,9 +4677,9 @@ bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) {
46764677
// It is convenient that such instructions don't have src_modifiers operand
46774678
// for src operands that don't allow neg because they also don't allow opsel.
46784679

4679-
int SrcMods[3] = {AMDGPU::OpName::src0_modifiers,
4680-
AMDGPU::OpName::src1_modifiers,
4681-
AMDGPU::OpName::src2_modifiers};
4680+
const AMDGPU::OpName SrcMods[3] = {AMDGPU::OpName::src0_modifiers,
4681+
AMDGPU::OpName::src1_modifiers,
4682+
AMDGPU::OpName::src2_modifiers};
46824683

46834684
for (unsigned i = 0; i < 3; ++i) {
46844685
if (!AMDGPU::hasNamedOperand(Opc, SrcMods[i])) {
@@ -4805,9 +4806,9 @@ bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,
48054806
}
48064807

48074808
// Returns -1 if not a register, 0 if VGPR and 1 if AGPR.
4808-
static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,
4809+
static int IsAGPROperand(const MCInst &Inst, AMDGPU::OpName Name,
48094810
const MCRegisterInfo *MRI) {
4810-
int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx);
4811+
int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name);
48114812
if (OpIdx < 0)
48124813
return -1;
48134814

@@ -4828,12 +4829,13 @@ bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
48284829
SIInstrFlags::DS)) == 0)
48294830
return true;
48304831

4831-
uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
4832-
: AMDGPU::OpName::vdata;
4832+
AMDGPU::OpName DataName = (TSFlags & SIInstrFlags::DS)
4833+
? AMDGPU::OpName::data0
4834+
: AMDGPU::OpName::vdata;
48334835

48344836
const MCRegisterInfo *MRI = getMRI();
48354837
int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI);
4836-
int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI);
4838+
int DataAreg = IsAGPROperand(Inst, DataName, MRI);
48374839

48384840
if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) {
48394841
int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI);
@@ -8647,9 +8649,8 @@ static void cvtVOP3DstOpSelOnly(MCInst &Inst, const MCRegisterInfo &MRI) {
86478649
return;
86488650

86498651
int SrcNum;
8650-
const int Ops[] = { AMDGPU::OpName::src0,
8651-
AMDGPU::OpName::src1,
8652-
AMDGPU::OpName::src2 };
8652+
const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
8653+
AMDGPU::OpName::src2};
86538654
for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);
86548655
++SrcNum)
86558656
;
@@ -8771,12 +8772,11 @@ void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
87718772
if (OpSelIdx == -1)
87728773
return;
87738774

8774-
const int Ops[] = { AMDGPU::OpName::src0,
8775-
AMDGPU::OpName::src1,
8776-
AMDGPU::OpName::src2 };
8777-
const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
8778-
AMDGPU::OpName::src1_modifiers,
8779-
AMDGPU::OpName::src2_modifiers };
8775+
const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
8776+
AMDGPU::OpName::src2};
8777+
const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
8778+
AMDGPU::OpName::src1_modifiers,
8779+
AMDGPU::OpName::src2_modifiers};
87808780

87818781
unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
87828782

@@ -8912,12 +8912,11 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
89128912
if (NegHiIdx != -1)
89138913
addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);
89148914

8915-
const int Ops[] = { AMDGPU::OpName::src0,
8916-
AMDGPU::OpName::src1,
8917-
AMDGPU::OpName::src2 };
8918-
const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
8919-
AMDGPU::OpName::src1_modifiers,
8920-
AMDGPU::OpName::src2_modifiers };
8915+
const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
8916+
AMDGPU::OpName::src2};
8917+
const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
8918+
AMDGPU::OpName::src1_modifiers,
8919+
AMDGPU::OpName::src2_modifiers};
89218920

89228921
unsigned OpSel = 0;
89238922
unsigned OpSelHi = 0;
@@ -8980,7 +8979,8 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
89808979
}
89818980

89828981
static void addSrcModifiersAndSrc(MCInst &Inst, const OperandVector &Operands,
8983-
unsigned i, unsigned Opc, unsigned OpName) {
8982+
unsigned i, unsigned Opc,
8983+
AMDGPU::OpName OpName) {
89848984
if (AMDGPU::getNamedOperandIdx(Opc, OpName) != -1)
89858985
((AMDGPUOperand &)*Operands[i]).addRegOrImmWithFPInputModsOperands(Inst, 2);
89868986
else

‎llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,7 @@ class GCNDPPCombine {
7070
RegSubRegPair CombOldVGPR, bool CombBCZ,
7171
bool IsShrinkable) const;
7272

73-
bool hasNoImmOrEqual(MachineInstr &MI,
74-
unsigned OpndName,
75-
int64_t Value,
73+
bool hasNoImmOrEqual(MachineInstr &MI, AMDGPU::OpName OpndName, int64_t Value,
7674
int64_t Mask = -1) const;
7775

7876
bool combineDPPMov(MachineInstr &MI) const;
@@ -513,7 +511,7 @@ MachineInstr *GCNDPPCombine::createDPPInst(
513511

514512
// returns true if MI doesn't have OpndName immediate operand or the
515513
// operand has Value
516-
bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, unsigned OpndName,
514+
bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, AMDGPU::OpName OpndName,
517515
int64_t Value, int64_t Mask) const {
518516
auto *Imm = TII->getNamedOperand(MI, OpndName);
519517
if (!Imm)

‎llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1310,7 +1310,7 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
13101310
if (!SIInstrInfo::isVALU(*MI))
13111311
return false;
13121312

1313-
unsigned SDSTName;
1313+
AMDGPU::OpName SDSTName;
13141314
switch (MI->getOpcode()) {
13151315
case AMDGPU::V_READLANE_B32:
13161316
case AMDGPU::V_READFIRSTLANE_B32:

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1205,7 +1205,7 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
12051205
int NumOps = 0;
12061206
int Ops[3];
12071207

1208-
std::pair<int, int> MOps[] = {
1208+
std::pair<AMDGPU::OpName, AMDGPU::OpName> MOps[] = {
12091209
{AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0},
12101210
{AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1},
12111211
{AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}};
@@ -1226,7 +1226,7 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
12261226
MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsWMMA) {
12271227
NumOps = 0;
12281228
int DefaultValue = Mod == SISrcMods::OP_SEL_1;
1229-
for (int OpName :
1229+
for (AMDGPU::OpName OpName :
12301230
{AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
12311231
AMDGPU::OpName::src2_modifiers}) {
12321232
int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -340,14 +340,13 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
340340

341341
uint64_t AMDGPUMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
342342
using namespace AMDGPU::VOP3PEncoding;
343-
using namespace AMDGPU::OpName;
344343

345-
if (AMDGPU::hasNamedOperand(Opcode, op_sel_hi)) {
346-
if (AMDGPU::hasNamedOperand(Opcode, src2))
344+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::op_sel_hi)) {
345+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2))
347346
return 0;
348-
if (AMDGPU::hasNamedOperand(Opcode, src1))
347+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src1))
349348
return OP_SEL_HI_2;
350-
if (AMDGPU::hasNamedOperand(Opcode, src0))
349+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0))
351350
return OP_SEL_HI_1 | OP_SEL_HI_2;
352351
}
353352
return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,6 @@ createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
5050
#include "AMDGPUGenRegisterInfo.inc"
5151

5252
#define GET_INSTRINFO_ENUM
53-
#define GET_INSTRINFO_OPERAND_ENUM
5453
#define GET_INSTRINFO_MC_HELPER_DECLS
5554
#include "AMDGPUGenInstrInfo.inc"
5655

‎llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCTargetDesc.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,6 @@ MCInstrInfo *createR600MCInstrInfo();
3232
#include "R600GenRegisterInfo.inc"
3333

3434
#define GET_INSTRINFO_ENUM
35-
#define GET_INSTRINFO_OPERAND_ENUM
3635
#define GET_INSTRINFO_SCHED_ENUM
3736
#define GET_INSTRINFO_MC_HELPER_DECLS
3837
#include "R600GenInstrInfo.inc"

‎llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
3131
const R600InstrInfo *TII = nullptr;
3232

3333
void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
34-
unsigned Op);
34+
R600::OpName Op);
3535

3636
public:
3737
static char ID;
@@ -61,7 +61,8 @@ FunctionPass *llvm::createR600ExpandSpecialInstrsPass() {
6161
}
6262

6363
void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
64-
const MachineInstr *OldMI, unsigned Op) {
64+
const MachineInstr *OldMI,
65+
R600::OpName Op) {
6566
int OpIdx = TII->getOperandIdx(*OldMI, Op);
6667
if (OpIdx > -1) {
6768
uint64_t Val = OldMI->getOperand(OpIdx).getImm();

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