fixup! [AArch64][GlobalISel] Legalize G_VECREDUCE_{MIN/MAX}

Author: chuongg3

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

@@ -173,6 +173,10 @@ def : GINodeEquiv<G_VECREDUCE_FMAX, vecreduce_fmax>;
 def : GINodeEquiv<G_VECREDUCE_FMIN, vecreduce_fmin>;
 def : GINodeEquiv<G_VECREDUCE_FMAXIMUM, vecreduce_fmaximum>;
 def : GINodeEquiv<G_VECREDUCE_FMINIMUM, vecreduce_fminimum>;
+def : GINodeEquiv<G_VECREDUCE_UMIN, vecreduce_umin>;
+def : GINodeEquiv<G_VECREDUCE_UMAX, vecreduce_umax>;
+def : GINodeEquiv<G_VECREDUCE_SMIN, vecreduce_smin>;
+def : GINodeEquiv<G_VECREDUCE_SMAX, vecreduce_smax>;
 
 def : GINodeEquiv<G_STRICT_FADD, strict_fadd>;
 def : GINodeEquiv<G_STRICT_FSUB, strict_fsub>;

llvm/lib/Target/AArch64/AArch64InstrGISel.td

@@ -274,11 +274,6 @@ def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
 
 def : GINodeEquiv<G_PREFETCH, AArch64Prefetch>;
 
-def : GINodeEquiv<G_VECREDUCE_UMIN, vecreduce_umin>;
-def : GINodeEquiv<G_VECREDUCE_UMAX, vecreduce_umax>;
-def : GINodeEquiv<G_VECREDUCE_SMIN, vecreduce_smin>;
-def : GINodeEquiv<G_VECREDUCE_SMAX, vecreduce_smax>;
-
 // These are patterns that we only use for GlobalISel via the importer.
 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
                      (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -6702,9 +6702,10 @@ defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
           (UMINPv2i32 V64:$Rn, V64:$Rn)>;
 
-// For vecreduce_{opc}
+// For vecreduce_{opc} used by GlobalISel, not SDAG at the moment
+// because GlobalISel allows us to specify the return register to be a FPR
 multiclass SIMDAcrossLanesVecReductionIntrinsic<string baseOpc,
-                                            SDPatternOperator opNode> {
+                                               SDPatternOperator opNode> {
 def : Pat<(i8 (opNode (v8i8 FPR64:$Rn))),
           (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) FPR64:$Rn)>;
 
@@ -6719,9 +6720,9 @@ def : Pat<(i16 (opNode (v8i16 FPR128:$Rn))),
 
 def : Pat<(i32 (opNode (v4i32 V128:$Rn))), 
           (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn)>;
-
 }
 
+// For v2i32 source type, the pairwise instruction can be used instead
 defm : SIMDAcrossLanesVecReductionIntrinsic<"UMINV", vecreduce_umin>;
 def : Pat<(i32 (vecreduce_umin (v2i32 V64:$Rn))), 
           (i32 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub))>;