Skip to content

Commit 05f0541

Browse files
committed
[DAG] combineVSelectWithAllOnesOrZeros - reusing existing VT. NFC.
1 parent 3e7ef03 commit 05f0541

File tree

1 file changed

+3
-4
lines changed

1 file changed

+3
-4
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13074,12 +13074,11 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
1307413074
const TargetLowering &TLI,
1307513075
SelectionDAG &DAG,
1307613076
const SDLoc &DL) {
13077-
if (!TLI.isTypeLegal(TVal.getValueType()))
13077+
EVT VT = TVal.getValueType();
13078+
if (!TLI.isTypeLegal(VT))
1307813079
return SDValue();
1307913080

13080-
EVT VT = TVal.getValueType();
1308113081
EVT CondVT = Cond.getValueType();
13082-
1308313082
assert(CondVT.isVector() && "Vector select expects a vector selector!");
1308413083

1308513084
bool IsTAllZero = ISD::isBuildVectorAllZeros(TVal.getNode());
@@ -13110,7 +13109,7 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
1311013109
}
1311113110

1311213111
// To use the condition operand as a bitwise mask, it must have elements that
13113-
// are the same size as the select elements. Ie, the condition operand must
13112+
// are the same size as the select elements. i.e, the condition operand must
1311413113
// have already been promoted from the IR select condition type <N x i1>.
1311513114
// Don't check if the types themselves are equal because that excludes
1311613115
// vector floating-point selects.

0 commit comments

Comments
 (0)