[AMDGPU] Make use of divideCeil. NFC.

Author: jayfoad

llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp

@@ -159,8 +159,7 @@ unsigned CFStack::getSubEntrySize(CFStack::StackItem Item) {
 }
 
 void CFStack::updateMaxStackSize() {
-  unsigned CurrentStackSize =
-      CurrentEntries + (alignTo(CurrentSubEntries, 4) / 4);
+  unsigned CurrentStackSize = CurrentEntries + divideCeil(CurrentSubEntries, 4);
   MaxStackSize = std::max(CurrentStackSize, MaxStackSize);
 }
 

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

@@ -274,7 +274,7 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
 
   // \returns a DWORD offset of a \p SubReg
   unsigned getChannelFromSubReg(unsigned SubReg) const {
-    return SubReg ? alignTo(getSubRegIdxOffset(SubReg), 32) / 32 : 0;
+    return SubReg ? divideCeil(getSubRegIdxOffset(SubReg), 32) : 0;
   }
 
   // \returns a DWORD size of a \p SubReg

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

@@ -301,8 +301,7 @@ unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
 
 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI,
                           unsigned FlatWorkGroupSize) {
-  return alignTo(getMaxWavesPerCU(STI, FlatWorkGroupSize),
-                 getEUsPerCU(STI)) / getEUsPerCU(STI);
+  return divideCeil(getMaxWavesPerCU(STI, FlatWorkGroupSize), getEUsPerCU(STI));
 }
 
 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI) {
@@ -316,8 +315,7 @@ unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI) {
 
 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
                               unsigned FlatWorkGroupSize) {
-  return alignTo(FlatWorkGroupSize, getWavefrontSize(STI)) /
-                 getWavefrontSize(STI);
+  return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI));
 }
 
 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {