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sgundapayuxuanchen1997
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[AMDGPU] Implement llvm.lround intrinsic lowering. (#98970)
Summary: This patch enables the target-independent lowering of llvm.lround via GlobalISel. For SelectionDAG, the instrinsic is custom lowered for AMDGPU. In order to support vector floating point input for llvm.lround, this patch extends the target independent APIs and provide support for scalarizing. pr98950 is needed to let verifier allow vector floating point types Test Plan: Reviewers: Subscribers: Tasks: Tags: Differential Revision: https://phabricator.intern.facebook.com/D60251041
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llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3881,6 +3881,17 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
38813881
return lowerFMad(MI);
38823882
case TargetOpcode::G_FFLOOR:
38833883
return lowerFFloor(MI);
3884+
case TargetOpcode::G_LROUND:
3885+
case TargetOpcode::G_LLROUND: {
3886+
Register DstReg = MI.getOperand(0).getReg();
3887+
Register SrcReg = MI.getOperand(1).getReg();
3888+
LLT SrcTy = MRI.getType(SrcReg);
3889+
auto Round = MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND, {SrcTy},
3890+
{SrcReg});
3891+
MIRBuilder.buildFPTOSI(DstReg, Round);
3892+
MI.eraseFromParent();
3893+
return Legalized;
3894+
}
38843895
case TargetOpcode::G_INTRINSIC_ROUND:
38853896
return lowerIntrinsicRound(MI);
38863897
case TargetOpcode::G_FRINT: {

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3439,6 +3439,16 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
34393439
case ISD::FP_TO_UINT_SAT:
34403440
Results.push_back(TLI.expandFP_TO_INT_SAT(Node, DAG));
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break;
3442+
case ISD::LROUND:
3443+
case ISD::LLROUND: {
3444+
SDValue Arg = Node->getOperand(0);
3445+
EVT ArgVT = Arg.getValueType();
3446+
EVT ResVT = Node->getValueType(0);
3447+
SDLoc dl(Node);
3448+
SDValue RoundNode = DAG.getNode(ISD::FROUND, dl, ArgVT, Arg);
3449+
Results.push_back(DAG.getNode(ISD::FP_TO_SINT, dl, ResVT, RoundNode));
3450+
break;
3451+
}
34423452
case ISD::VAARG:
34433453
Results.push_back(DAG.expandVAArg(Node));
34443454
Results.push_back(Results[0].getValue(1));

llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -824,13 +824,16 @@ void TargetLoweringBase::initActions() {
824824
Expand);
825825

826826
// These library functions default to expand.
827-
setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
828-
ISD::FEXP, ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR,
829-
ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC,
830-
ISD::LROUND, ISD::LLROUND, ISD::LRINT, ISD::LLRINT,
831-
ISD::FROUNDEVEN, ISD::FTAN, ISD::FACOS, ISD::FASIN,
832-
ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH},
833-
{MVT::f32, MVT::f64, MVT::f128}, Expand);
827+
setOperationAction(
828+
{ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP,
829+
ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL,
830+
ISD::FRINT, ISD::FTRUNC, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN,
831+
ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
832+
ISD::FSINH, ISD::FTANH},
833+
{MVT::f32, MVT::f64, MVT::f128}, Expand);
834+
835+
setOperationAction({ISD::LROUND, ISD::LLROUND},
836+
{MVT::f32, MVT::f64, MVT::f128}, LibCall);
834837

835838
setOperationAction({ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN, ISD::FCOSH,
836839
ISD::FSINH, ISD::FTANH},

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -397,6 +397,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
397397

398398
setOperationAction(ISD::FLOG2, MVT::f32, Custom);
399399
setOperationAction(ISD::FROUND, {MVT::f32, MVT::f64}, Custom);
400+
setOperationAction({ISD::LROUND, ISD::LLROUND},
401+
{MVT::f16, MVT::f32, MVT::f64}, Expand);
400402

401403
setOperationAction(
402404
{ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32,

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1131,6 +1131,11 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
11311131
.scalarize(0)
11321132
.lower();
11331133

1134+
getActionDefinitionsBuilder({G_LROUND, G_LLROUND})
1135+
.clampScalar(0, S16, S64)
1136+
.scalarize(0)
1137+
.lower();
1138+
11341139
getActionDefinitionsBuilder(G_INTRINSIC_FPTRUNC_ROUND)
11351140
.customFor({S16, S32})
11361141
.scalarize(0)

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -849,8 +849,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
849849
setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
850850
setOperationAction(ISD::FROUNDEVEN, MVT::f80, Expand);
851851
setOperationAction(ISD::FMA, MVT::f80, Expand);
852-
setOperationAction(ISD::LROUND, MVT::f80, Expand);
853-
setOperationAction(ISD::LLROUND, MVT::f80, Expand);
852+
setOperationAction(ISD::LROUND, MVT::f80, LibCall);
853+
setOperationAction(ISD::LLROUND, MVT::f80, LibCall);
854854
setOperationAction(ISD::LRINT, MVT::f80, Custom);
855855
setOperationAction(ISD::LLRINT, MVT::f80, Custom);
856856

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