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davemgreendavemgreen
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[AArch64] Regenerate complex-int-to-fp.ll. NFC
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‎llvm/test/CodeGen/AArch64/complex-int-to-fp.ll

Lines changed: 95 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,14 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
23

3-
; CHECK: autogen_SD19655
4-
; CHECK: scvtf
5-
; CHECK: ret
64
define void @autogen_SD19655(ptr %addr, ptr %addrfloat) {
5+
; CHECK-LABEL: autogen_SD19655:
6+
; CHECK: // %bb.0:
7+
; CHECK-NEXT: ldr q0, [x0]
8+
; CHECK-NEXT: scvtf.2d v0, v0
9+
; CHECK-NEXT: fcvtn v0.2s, v0.2d
10+
; CHECK-NEXT: str d0, [x1]
11+
; CHECK-NEXT: ret
712
%T = load <2 x i64>, ptr %addr
813
%F = sitofp <2 x i64> %T to <2 x float>
914
store <2 x float> %F, ptr %addrfloat
@@ -12,152 +17,182 @@ define void @autogen_SD19655(ptr %addr, ptr %addrfloat) {
1217

1318
define <2 x double> @test_signed_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
1419
; CHECK-LABEL: test_signed_v2i32_to_v2f64:
15-
; CHECK: sshll.2d [[VAL64:v[0-9]+]], v0, #0
16-
; CHECK-NEXT: scvtf.2d v0, [[VAL64]]
17-
; CHECK-NEXT: ret
20+
; CHECK: // %bb.0:
21+
; CHECK-NEXT: sshll.2d v0, v0, #0
22+
; CHECK-NEXT: scvtf.2d v0, v0
23+
; CHECK-NEXT: ret
1824
%conv = sitofp <2 x i32> %v to <2 x double>
1925
ret <2 x double> %conv
2026
}
2127

2228
define <2 x double> @test_unsigned_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone {
23-
; CHECK-LABEL: test_unsigned_v2i32_to_v2f64
24-
; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
25-
; CHECK-NEXT: ucvtf.2d v0, [[VAL64]]
26-
; CHECK-NEXT: ret
29+
; CHECK-LABEL: test_unsigned_v2i32_to_v2f64:
30+
; CHECK: // %bb.0:
31+
; CHECK-NEXT: ushll.2d v0, v0, #0
32+
; CHECK-NEXT: ucvtf.2d v0, v0
33+
; CHECK-NEXT: ret
2734
%conv = uitofp <2 x i32> %v to <2 x double>
2835
ret <2 x double> %conv
2936
}
3037

3138
define <2 x double> @test_signed_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
3239
; CHECK-LABEL: test_signed_v2i16_to_v2f64:
33-
; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
34-
; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
35-
; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
36-
; CHECK: scvtf.2d v0, [[VAL64]]
40+
; CHECK: // %bb.0:
41+
; CHECK-NEXT: shl.2s v0, v0, #16
42+
; CHECK-NEXT: sshr.2s v0, v0, #16
43+
; CHECK-NEXT: sshll.2d v0, v0, #0
44+
; CHECK-NEXT: scvtf.2d v0, v0
45+
; CHECK-NEXT: ret
3746

3847
%conv = sitofp <2 x i16> %v to <2 x double>
3948
ret <2 x double> %conv
4049
}
4150
define <2 x double> @test_unsigned_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone {
42-
; CHECK-LABEL: test_unsigned_v2i16_to_v2f64
43-
; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
44-
; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
45-
; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
46-
; CHECK: ucvtf.2d v0, [[VAL64]]
51+
; CHECK-LABEL: test_unsigned_v2i16_to_v2f64:
52+
; CHECK: // %bb.0:
53+
; CHECK-NEXT: movi d1, #0x00ffff0000ffff
54+
; CHECK-NEXT: and.8b v0, v0, v1
55+
; CHECK-NEXT: ushll.2d v0, v0, #0
56+
; CHECK-NEXT: ucvtf.2d v0, v0
57+
; CHECK-NEXT: ret
4758

4859
%conv = uitofp <2 x i16> %v to <2 x double>
4960
ret <2 x double> %conv
5061
}
5162

5263
define <2 x double> @test_signed_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
5364
; CHECK-LABEL: test_signed_v2i8_to_v2f64:
54-
; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
55-
; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
56-
; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
57-
; CHECK: scvtf.2d v0, [[VAL64]]
65+
; CHECK: // %bb.0:
66+
; CHECK-NEXT: shl.2s v0, v0, #24
67+
; CHECK-NEXT: sshr.2s v0, v0, #24
68+
; CHECK-NEXT: sshll.2d v0, v0, #0
69+
; CHECK-NEXT: scvtf.2d v0, v0
70+
; CHECK-NEXT: ret
5871

5972
%conv = sitofp <2 x i8> %v to <2 x double>
6073
ret <2 x double> %conv
6174
}
6275
define <2 x double> @test_unsigned_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone {
63-
; CHECK-LABEL: test_unsigned_v2i8_to_v2f64
64-
; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
65-
; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
66-
; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
67-
; CHECK: ucvtf.2d v0, [[VAL64]]
76+
; CHECK-LABEL: test_unsigned_v2i8_to_v2f64:
77+
; CHECK: // %bb.0:
78+
; CHECK-NEXT: movi d1, #0x0000ff000000ff
79+
; CHECK-NEXT: and.8b v0, v0, v1
80+
; CHECK-NEXT: ushll.2d v0, v0, #0
81+
; CHECK-NEXT: ucvtf.2d v0, v0
82+
; CHECK-NEXT: ret
6883

6984
%conv = uitofp <2 x i8> %v to <2 x double>
7085
ret <2 x double> %conv
7186
}
7287

7388
define <2 x float> @test_signed_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone {
7489
; CHECK-LABEL: test_signed_v2i64_to_v2f32:
75-
; CHECK: scvtf.2d [[VAL64:v[0-9]+]], v0
76-
; CHECK: fcvtn v0.2s, [[VAL64]].2d
90+
; CHECK: // %bb.0:
91+
; CHECK-NEXT: scvtf.2d v0, v0
92+
; CHECK-NEXT: fcvtn v0.2s, v0.2d
93+
; CHECK-NEXT: ret
7794

7895
%conv = sitofp <2 x i64> %v to <2 x float>
7996
ret <2 x float> %conv
8097
}
8198
define <2 x float> @test_unsigned_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone {
82-
; CHECK-LABEL: test_unsigned_v2i64_to_v2f32
83-
; CHECK: ucvtf.2d [[VAL64:v[0-9]+]], v0
84-
; CHECK: fcvtn v0.2s, [[VAL64]].2d
99+
; CHECK-LABEL: test_unsigned_v2i64_to_v2f32:
100+
; CHECK: // %bb.0:
101+
; CHECK-NEXT: ucvtf.2d v0, v0
102+
; CHECK-NEXT: fcvtn v0.2s, v0.2d
103+
; CHECK-NEXT: ret
85104

86105
%conv = uitofp <2 x i64> %v to <2 x float>
87106
ret <2 x float> %conv
88107
}
89108

90109
define <2 x float> @test_signed_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone {
91110
; CHECK-LABEL: test_signed_v2i16_to_v2f32:
92-
; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16
93-
; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16
94-
; CHECK: scvtf.2s v0, [[VAL32]]
111+
; CHECK: // %bb.0:
112+
; CHECK-NEXT: shl.2s v0, v0, #16
113+
; CHECK-NEXT: sshr.2s v0, v0, #16
114+
; CHECK-NEXT: scvtf.2s v0, v0
115+
; CHECK-NEXT: ret
95116

96117
%conv = sitofp <2 x i16> %v to <2 x float>
97118
ret <2 x float> %conv
98119
}
99120
define <2 x float> @test_unsigned_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone {
100-
; CHECK-LABEL: test_unsigned_v2i16_to_v2f32
101-
; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff
102-
; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
103-
; CHECK: ucvtf.2s v0, [[VAL32]]
121+
; CHECK-LABEL: test_unsigned_v2i16_to_v2f32:
122+
; CHECK: // %bb.0:
123+
; CHECK-NEXT: movi d1, #0x00ffff0000ffff
124+
; CHECK-NEXT: and.8b v0, v0, v1
125+
; CHECK-NEXT: ucvtf.2s v0, v0
126+
; CHECK-NEXT: ret
104127

105128
%conv = uitofp <2 x i16> %v to <2 x float>
106129
ret <2 x float> %conv
107130
}
108131

109132
define <2 x float> @test_signed_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone {
110133
; CHECK-LABEL: test_signed_v2i8_to_v2f32:
111-
; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24
112-
; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24
113-
; CHECK: scvtf.2s v0, [[VAL32]]
134+
; CHECK: // %bb.0:
135+
; CHECK-NEXT: shl.2s v0, v0, #24
136+
; CHECK-NEXT: sshr.2s v0, v0, #24
137+
; CHECK-NEXT: scvtf.2s v0, v0
138+
; CHECK-NEXT: ret
114139

115140
%conv = sitofp <2 x i8> %v to <2 x float>
116141
ret <2 x float> %conv
117142
}
118143
define <2 x float> @test_unsigned_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone {
119-
; CHECK-LABEL: test_unsigned_v2i8_to_v2f32
120-
; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff
121-
; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]]
122-
; CHECK: ucvtf.2s v0, [[VAL32]]
144+
; CHECK-LABEL: test_unsigned_v2i8_to_v2f32:
145+
; CHECK: // %bb.0:
146+
; CHECK-NEXT: movi d1, #0x0000ff000000ff
147+
; CHECK-NEXT: and.8b v0, v0, v1
148+
; CHECK-NEXT: ucvtf.2s v0, v0
149+
; CHECK-NEXT: ret
123150

124151
%conv = uitofp <2 x i8> %v to <2 x float>
125152
ret <2 x float> %conv
126153
}
127154

128155
define <4 x float> @test_signed_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
129156
; CHECK-LABEL: test_signed_v4i16_to_v4f32:
130-
; CHECK: sshll.4s [[VAL32:v[0-9]+]], v0, #0
131-
; CHECK: scvtf.4s v0, [[VAL32]]
157+
; CHECK: // %bb.0:
158+
; CHECK-NEXT: sshll.4s v0, v0, #0
159+
; CHECK-NEXT: scvtf.4s v0, v0
160+
; CHECK-NEXT: ret
132161

133162
%conv = sitofp <4 x i16> %v to <4 x float>
134163
ret <4 x float> %conv
135164
}
136165

137166
define <4 x float> @test_unsigned_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone {
138-
; CHECK-LABEL: test_unsigned_v4i16_to_v4f32
139-
; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
140-
; CHECK: ucvtf.4s v0, [[VAL32]]
167+
; CHECK-LABEL: test_unsigned_v4i16_to_v4f32:
168+
; CHECK: // %bb.0:
169+
; CHECK-NEXT: ushll.4s v0, v0, #0
170+
; CHECK-NEXT: ucvtf.4s v0, v0
171+
; CHECK-NEXT: ret
141172

142173
%conv = uitofp <4 x i16> %v to <4 x float>
143174
ret <4 x float> %conv
144175
}
145176

146177
define <4 x float> @test_signed_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
147178
; CHECK-LABEL: test_signed_v4i8_to_v4f32:
148-
; CHECK: shl.4h [[TMP:v[0-9]+]], v0, #8
149-
; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8
150-
; CHECK: sshll.4s [[VAL32:v[0-9]+]], [[VAL16]], #0
151-
; CHECK: scvtf.4s v0, [[VAL32]]
179+
; CHECK: // %bb.0:
180+
; CHECK-NEXT: shl.4h v0, v0, #8
181+
; CHECK-NEXT: sshr.4h v0, v0, #8
182+
; CHECK-NEXT: sshll.4s v0, v0, #0
183+
; CHECK-NEXT: scvtf.4s v0, v0
184+
; CHECK-NEXT: ret
152185

153186
%conv = sitofp <4 x i8> %v to <4 x float>
154187
ret <4 x float> %conv
155188
}
156189
define <4 x float> @test_unsigned_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone {
157-
; CHECK-LABEL: test_unsigned_v4i8_to_v4f32
158-
; CHECK: bic.4h v0, #255, lsl #8
159-
; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
160-
; CHECK: ucvtf.4s v0, [[VAL32]]
190+
; CHECK-LABEL: test_unsigned_v4i8_to_v4f32:
191+
; CHECK: // %bb.0:
192+
; CHECK-NEXT: bic.4h v0, #255, lsl #8
193+
; CHECK-NEXT: ushll.4s v0, v0, #0
194+
; CHECK-NEXT: ucvtf.4s v0, v0
195+
; CHECK-NEXT: ret
161196

162197
%conv = uitofp <4 x i8> %v to <4 x float>
163198
ret <4 x float> %conv

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