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[RISCV] Fix the order of arguments of setTruncStoreAction and setLoadExtAction (#73090)
The first argument of setTruncStoreAction/setLoadExtAction should be Value VT instead of Memory VT.
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -751,9 +751,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
751751
// Expand all extending loads to types larger than this, and truncating
752752
// stores from types larger than this.
753753
for (MVT OtherVT : MVT::integer_scalable_vector_valuetypes()) {
754-
setTruncStoreAction(OtherVT, VT, Expand);
755-
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, OtherVT,
756-
VT, Expand);
754+
setTruncStoreAction(VT, OtherVT, Expand);
755+
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, VT,
756+
OtherVT, Expand);
757757
}
758758

759759
setOperationAction({ISD::VP_FP_TO_SINT, ISD::VP_FP_TO_UINT,
@@ -843,8 +843,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
843843

844844
for (MVT OtherVT : MVT::integer_scalable_vector_valuetypes()) {
845845
setTruncStoreAction(VT, OtherVT, Expand);
846-
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, OtherVT,
847-
VT, Expand);
846+
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, VT,
847+
OtherVT, Expand);
848848
}
849849

850850
setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom);
@@ -1074,8 +1074,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
10741074
setOperationAction(Op, VT, Expand);
10751075
for (MVT OtherVT : MVT::integer_fixedlen_vector_valuetypes()) {
10761076
setTruncStoreAction(VT, OtherVT, Expand);
1077-
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD},
1078-
OtherVT, VT, Expand);
1077+
setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, VT,
1078+
OtherVT, Expand);
10791079
}
10801080

10811081
// Custom lower fixed vector undefs to scalable vector undefs to avoid

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