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[AMDGPU] Add test for fpext & fptrunc with bf16. (#85909)
Authored-by: Pravin Jagtap <[email protected]>
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‎llvm/test/CodeGen/AMDGPU/bf16-conversions.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -march=amdgcn -mcpu=gfx940 < %s | FileCheck --check-prefixes=GCN %s
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; TODO: Add global-isel when it can support bf16
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define amdgpu_ps float @v_test_cvt_bf16_f32_v(bfloat %v) {
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; GCN-LABEL: v_test_cvt_bf16_f32_v:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
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; GCN-NEXT: ; return to shader part epilog
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%cvt = fpext bfloat %v to float
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ret float %cvt
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}
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define amdgpu_ps float @v_test_cvt_bf16_f32_s(bfloat inreg %v) {
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; GCN-LABEL: v_test_cvt_bf16_f32_s:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_lshl_b32 s0, s0, 16
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: ; return to shader part epilog
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%cvt = fpext bfloat %v to float
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ret float %cvt
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}
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define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_v(<2 x float> %src) {
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; GCN-LABEL: v_test_cvt_v2f32_v2bf16_v:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_bfe_u32 v2, v0, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v2, v2, v0, s0
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; GCN-NEXT: v_or_b32_e32 v3, 0x400000, v0
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; GCN-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
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; GCN-NEXT: v_bfe_u32 v2, v1, 16, 1
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; GCN-NEXT: v_add3_u32 v2, v2, v1, s0
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; GCN-NEXT: v_or_b32_e32 v3, 0x400000, v1
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; GCN-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
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; GCN-NEXT: s_mov_b32 s0, 0x7060302
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
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; GCN-NEXT: v_perm_b32 v0, v1, v0, s0
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; GCN-NEXT: ; return to shader part epilog
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%res = fptrunc <2 x float> %src to <2 x bfloat>
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%cast = bitcast <2 x bfloat> %res to float
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ret float %cast
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}
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define amdgpu_ps float @v_test_cvt_v2f32_v2bf16_s(<2 x float> inreg %src) {
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; GCN-LABEL: v_test_cvt_v2f32_v2bf16_s:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_bfe_u32 s2, s1, 0x10010
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; GCN-NEXT: s_add_i32 s2, s2, s1
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; GCN-NEXT: s_or_b32 s4, s1, 0x400000
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; GCN-NEXT: s_add_i32 s5, s2, 0x7fff
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; GCN-NEXT: v_cmp_u_f32_e64 s[2:3], s1, s1
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; GCN-NEXT: s_and_b64 s[2:3], s[2:3], exec
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; GCN-NEXT: s_cselect_b32 s2, s4, s5
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; GCN-NEXT: s_bfe_u32 s1, s0, 0x10010
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; GCN-NEXT: s_add_i32 s1, s1, s0
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; GCN-NEXT: s_or_b32 s3, s0, 0x400000
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; GCN-NEXT: s_add_i32 s4, s1, 0x7fff
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; GCN-NEXT: v_cmp_u_f32_e64 s[0:1], s0, s0
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; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
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; GCN-NEXT: s_cselect_b32 s0, s3, s4
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; GCN-NEXT: s_pack_hh_b32_b16 s0, s0, s2
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: ; return to shader part epilog
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%res = fptrunc <2 x float> %src to <2 x bfloat>
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%cast = bitcast <2 x bfloat> %res to float
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ret float %cast
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}
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define amdgpu_ps float @v_test_cvt_f32_bf16_v(float %src) {
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; GCN-LABEL: v_test_cvt_f32_bf16_v:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_bfe_u32 v1, v0, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v1, v1, v0, s0
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; GCN-NEXT: v_or_b32_e32 v2, 0x400000, v0
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; GCN-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
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; GCN-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
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; GCN-NEXT: ; return to shader part epilog
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%trunc = fptrunc float %src to bfloat
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%ext = fpext bfloat %trunc to float
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ret float %ext
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}
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define amdgpu_ps float @v_test_cvt_v2f64_v2bf16_v(<2 x double> %src) {
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; GCN-LABEL: v_test_cvt_v2f64_v2bf16_v:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
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; GCN-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
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; GCN-NEXT: v_and_b32_e32 v7, 1, v6
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; GCN-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
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; GCN-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
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; GCN-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
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; GCN-NEXT: v_add_u32_e32 v4, v6, v4
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; GCN-NEXT: s_or_b64 vcc, s[0:1], vcc
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; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
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; GCN-NEXT: s_brev_b32 s4, 1
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; GCN-NEXT: v_and_or_b32 v5, v1, s4, v4
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; GCN-NEXT: v_bfe_u32 v4, v4, 16, 1
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; GCN-NEXT: s_movk_i32 s5, 0x7fff
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; GCN-NEXT: v_add3_u32 v4, v4, v5, s5
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; GCN-NEXT: v_or_b32_e32 v5, 0x400000, v5
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; GCN-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
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; GCN-NEXT: v_cvt_f32_f64_e64 v5, |v[2:3]|
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; GCN-NEXT: v_cvt_f64_f32_e32 v[0:1], v5
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; GCN-NEXT: v_and_b32_e32 v6, 1, v5
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; GCN-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[2:3]|, v[0:1]
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; GCN-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[2:3]|, v[0:1]
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
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; GCN-NEXT: v_cndmask_b32_e64 v0, -1, 1, s[2:3]
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; GCN-NEXT: v_add_u32_e32 v0, v5, v0
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; GCN-NEXT: s_or_b64 vcc, s[0:1], vcc
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; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
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; GCN-NEXT: v_and_or_b32 v1, v3, s4, v0
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; GCN-NEXT: v_bfe_u32 v0, v0, 16, 1
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; GCN-NEXT: v_add3_u32 v0, v0, v1, s5
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; GCN-NEXT: v_or_b32_e32 v1, 0x400000, v1
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; GCN-NEXT: v_cmp_u_f64_e32 vcc, v[2:3], v[2:3]
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; GCN-NEXT: s_mov_b32 s0, 0x7060302
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
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; GCN-NEXT: v_perm_b32 v0, v0, v4, s0
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; GCN-NEXT: ; return to shader part epilog
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%res = fptrunc <2 x double> %src to <2 x bfloat>
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%cast = bitcast <2 x bfloat> %res to float
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ret float %cast
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}
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define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
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; GCN-LABEL: fptrunc_f32_f32_to_v2bf16:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_bfe_u32 v2, v0, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v2, v2, v0, s0
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; GCN-NEXT: v_or_b32_e32 v3, 0x400000, v0
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; GCN-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
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; GCN-NEXT: v_bfe_u32 v2, v1, 16, 1
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; GCN-NEXT: v_add3_u32 v2, v2, v1, s0
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; GCN-NEXT: v_or_b32_e32 v3, 0x400000, v1
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; GCN-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
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; GCN-NEXT: s_mov_b32 s0, 0x7060302
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
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; GCN-NEXT: v_perm_b32 v0, v1, v0, s0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%a.cvt = fptrunc float %a to bfloat
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%b.cvt = fptrunc float %b to bfloat
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%v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
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%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
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%ret = bitcast <2 x bfloat> %v2.2 to float
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ret float %ret
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}
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define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16_mods(float %a, float %b) {
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; GCN-LABEL: fptrunc_f32_f32_to_v2bf16_mods:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v0
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; GCN-NEXT: v_bfe_u32 v3, v2, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v3, v3, v2, s0
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; GCN-NEXT: v_or_b32_e32 v2, 0x400000, v2
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; GCN-NEXT: v_cmp_u_f32_e64 vcc, -v0, -v0
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
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; GCN-NEXT: v_and_b32_e32 v2, 0x7fffffff, v1
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; GCN-NEXT: v_bfe_u32 v3, v2, 16, 1
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; GCN-NEXT: v_add3_u32 v3, v3, v2, s0
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; GCN-NEXT: v_or_b32_e32 v2, 0x400000, v2
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; GCN-NEXT: v_cmp_u_f32_e64 vcc, |v1|, |v1|
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; GCN-NEXT: s_mov_b32 s0, 0x7060302
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; GCN-NEXT: s_nop 0
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; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
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; GCN-NEXT: v_perm_b32 v0, v1, v0, s0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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%a.neg = fneg float %a
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%a.cvt = fptrunc float %a.neg to bfloat
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%b.abs = call float @llvm.fabs.f32(float %b)
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%b.cvt = fptrunc float %b.abs to bfloat
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%v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
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%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
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%ret = bitcast <2 x bfloat> %v2.2 to float
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ret float %ret
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}
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define amdgpu_ps void @fptrunc_f32_to_bf16(float %a, ptr %out) {
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; GCN-LABEL: fptrunc_f32_to_bf16:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_mov_b32_e32 v3, v2
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; GCN-NEXT: v_mov_b32_e32 v2, v1
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; GCN-NEXT: v_bfe_u32 v1, v0, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v1, v1, v0, s0
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; GCN-NEXT: v_or_b32_e32 v4, 0x400000, v0
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; GCN-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v4, vcc
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; GCN-NEXT: flat_store_short_d16_hi v[2:3], v0 sc0 sc1
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; GCN-NEXT: s_endpgm
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entry:
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%a.cvt = fptrunc float %a to bfloat
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store bfloat %a.cvt, ptr %out
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ret void
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}
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define amdgpu_ps void @fptrunc_f32_to_bf16_abs(float %a, ptr %out) {
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; GCN-LABEL: fptrunc_f32_to_bf16_abs:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_mov_b32_e32 v3, v2
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; GCN-NEXT: v_mov_b32_e32 v2, v1
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; GCN-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0
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; GCN-NEXT: v_bfe_u32 v4, v1, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v4, v4, v1, s0
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; GCN-NEXT: v_or_b32_e32 v1, 0x400000, v1
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; GCN-NEXT: v_cmp_u_f32_e64 vcc, |v0|, |v0|
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
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; GCN-NEXT: flat_store_short_d16_hi v[2:3], v0 sc0 sc1
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; GCN-NEXT: s_endpgm
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entry:
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%a.abs = call float @llvm.fabs.f32(float %a)
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%a.cvt = fptrunc float %a.abs to bfloat
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store bfloat %a.cvt, ptr %out
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ret void
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}
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define amdgpu_ps void @fptrunc_f32_to_bf16_neg(float %a, ptr %out) {
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; GCN-LABEL: fptrunc_f32_to_bf16_neg:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_mov_b32_e32 v3, v2
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; GCN-NEXT: v_mov_b32_e32 v2, v1
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; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v0
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; GCN-NEXT: v_bfe_u32 v4, v1, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v4, v4, v1, s0
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; GCN-NEXT: v_or_b32_e32 v1, 0x400000, v1
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; GCN-NEXT: v_cmp_u_f32_e64 vcc, -v0, -v0
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
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; GCN-NEXT: flat_store_short_d16_hi v[2:3], v0 sc0 sc1
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; GCN-NEXT: s_endpgm
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entry:
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%a.neg = fneg float %a
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%a.cvt = fptrunc float %a.neg to bfloat
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store bfloat %a.cvt, ptr %out
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ret void
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}
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define amdgpu_ps void @fptrunc_f64_to_bf16(double %a, ptr %out) {
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; GCN-LABEL: fptrunc_f64_to_bf16:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_cvt_f32_f64_e64 v6, |v[0:1]|
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; GCN-NEXT: v_cvt_f64_f32_e32 v[4:5], v6
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; GCN-NEXT: v_and_b32_e32 v7, 1, v6
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; GCN-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
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; GCN-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
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; GCN-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
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; GCN-NEXT: v_add_u32_e32 v4, v6, v4
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; GCN-NEXT: s_or_b64 vcc, s[0:1], vcc
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; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
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; GCN-NEXT: s_brev_b32 s0, 1
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; GCN-NEXT: v_and_or_b32 v5, v1, s0, v4
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; GCN-NEXT: v_bfe_u32 v4, v4, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v4, v4, v5, s0
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; GCN-NEXT: v_or_b32_e32 v5, 0x400000, v5
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; GCN-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
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; GCN-NEXT: flat_store_short_d16_hi v[2:3], v0 sc0 sc1
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; GCN-NEXT: s_endpgm
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entry:
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%a.cvt = fptrunc double %a to bfloat
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store bfloat %a.cvt, ptr %out
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ret void
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}
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define amdgpu_ps void @fptrunc_f64_to_bf16_neg(double %a, ptr %out) {
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; GCN-LABEL: fptrunc_f64_to_bf16_neg:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_cvt_f32_f64_e64 v7, |v[0:1]|
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; GCN-NEXT: v_cvt_f64_f32_e32 v[4:5], v7
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; GCN-NEXT: v_and_b32_e32 v8, 1, v7
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; GCN-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
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; GCN-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
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; GCN-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
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; GCN-NEXT: v_add_u32_e32 v4, v7, v4
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; GCN-NEXT: s_or_b64 vcc, s[0:1], vcc
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; GCN-NEXT: s_brev_b32 s4, 1
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; GCN-NEXT: v_xor_b32_e32 v6, 0x80000000, v1
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; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
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; GCN-NEXT: v_and_or_b32 v5, v6, s4, v4
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; GCN-NEXT: v_bfe_u32 v4, v4, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v4, v4, v5, s0
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; GCN-NEXT: v_or_b32_e32 v5, 0x400000, v5
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; GCN-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[0:1]
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
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; GCN-NEXT: flat_store_short_d16_hi v[2:3], v0 sc0 sc1
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; GCN-NEXT: s_endpgm
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entry:
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%a.neg = fneg double %a
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%a.cvt = fptrunc double %a.neg to bfloat
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store bfloat %a.cvt, ptr %out
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ret void
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}
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define amdgpu_ps void @fptrunc_f64_to_bf16_abs(double %a, ptr %out) {
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; GCN-LABEL: fptrunc_f64_to_bf16_abs:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_cvt_f32_f64_e64 v7, |v[0:1]|
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; GCN-NEXT: v_cvt_f64_f32_e32 v[4:5], v7
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; GCN-NEXT: v_and_b32_e32 v8, 1, v7
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; GCN-NEXT: v_cmp_gt_f64_e64 s[2:3], |v[0:1]|, v[4:5]
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; GCN-NEXT: v_cmp_nlg_f64_e64 s[0:1], |v[0:1]|, v[4:5]
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
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; GCN-NEXT: v_cndmask_b32_e64 v4, -1, 1, s[2:3]
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; GCN-NEXT: v_add_u32_e32 v4, v7, v4
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; GCN-NEXT: s_or_b64 vcc, s[0:1], vcc
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; GCN-NEXT: v_and_b32_e32 v6, 0x7fffffff, v1
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; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
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; GCN-NEXT: s_brev_b32 s0, 1
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; GCN-NEXT: v_and_or_b32 v5, v6, s0, v4
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; GCN-NEXT: v_bfe_u32 v4, v4, 16, 1
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; GCN-NEXT: s_movk_i32 s0, 0x7fff
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; GCN-NEXT: v_add3_u32 v4, v4, v5, s0
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; GCN-NEXT: v_or_b32_e32 v5, 0x400000, v5
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; GCN-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, |v[0:1]|
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; GCN-NEXT: s_nop 1
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; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
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; GCN-NEXT: flat_store_short_d16_hi v[2:3], v0 sc0 sc1
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; GCN-NEXT: s_endpgm
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entry:
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%a.abs = call double @llvm.fabs.f64(double %a)
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%a.cvt = fptrunc double %a.abs to bfloat
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store bfloat %a.cvt, ptr %out
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ret void
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}
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declare float @llvm.fabs.f32(float)
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declare double @llvm.fabs.f64(double)
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