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[InstCombine] Infer zext nneg flag directly
1 parent bd61126 commit 07958d9

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10 files changed

+38
-19
lines changed

10 files changed

+38
-19
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -542,7 +542,8 @@ static Instruction *foldCttzCtlz(IntrinsicInst &II, InstCombinerImpl &IC) {
542542
if (match(Op0, m_OneUse(m_ZExt(m_Value(X)))) && match(Op1, m_One())) {
543543
auto *Cttz = IC.Builder.CreateBinaryIntrinsic(Intrinsic::cttz, X,
544544
IC.Builder.getTrue());
545-
auto *ZextCttz = IC.Builder.CreateZExt(Cttz, II.getType());
545+
auto *ZextCttz = IC.Builder.CreateZExt(Cttz, II.getType(), /*Name*/ "",
546+
/*IsNonNeg*/ true);
546547
return IC.replaceInstUsesWith(II, ZextCttz);
547548
}
548549

@@ -639,7 +640,10 @@ static Instruction *foldCtpop(IntrinsicInst &II, InstCombinerImpl &IC) {
639640
// ctpop (zext X) --> zext (ctpop X)
640641
if (match(Op0, m_OneUse(m_ZExt(m_Value(X))))) {
641642
Value *NarrowPop = IC.Builder.CreateUnaryIntrinsic(Intrinsic::ctpop, X);
642-
return CastInst::Create(Instruction::ZExt, NarrowPop, Ty);
643+
Instruction *Zext = CastInst::Create(Instruction::ZExt, NarrowPop, Ty);
644+
if (X->getType()->getScalarSizeInBits() > 2)
645+
Zext->setNonNeg();
646+
return Zext;
643647
}
644648

645649
KnownBits Known(BitWidth);

‎llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1159,7 +1159,9 @@ Instruction *InstCombinerImpl::visitZExt(ZExtInst &Zext) {
11591159
APInt AndValue(APInt::getLowBitsSet(SrcSize, MidSize));
11601160
Constant *AndConst = ConstantInt::get(A->getType(), AndValue);
11611161
Value *And = Builder.CreateAnd(A, AndConst, CSrc->getName() + ".mask");
1162-
return new ZExtInst(And, DestTy);
1162+
auto *ZExt = new ZExtInst(And, DestTy);
1163+
ZExt->setNonNeg();
1164+
return ZExt;
11631165
}
11641166

11651167
if (SrcSize == DstSize) {

‎llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5913,7 +5913,9 @@ static Instruction *processUMulZExtIdiom(ICmpInst &I, Value *MulVal,
59135913
ConstantInt *CI = cast<ConstantInt>(BO->getOperand(1));
59145914
APInt ShortMask = CI->getValue().trunc(MulWidth);
59155915
Value *ShortAnd = Builder.CreateAnd(Mul, ShortMask);
5916-
Value *Zext = Builder.CreateZExt(ShortAnd, BO->getType());
5916+
Value *Zext =
5917+
Builder.CreateZExt(ShortAnd, BO->getType(), /*Name*/ "",
5918+
/*IsNonNeg*/ ShortMask.isNonNegative());
59175919
IC.replaceInstUsesWith(*BO, Zext);
59185920
} else {
59195921
llvm_unreachable("Unexpected Binary operation");

‎llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1243,7 +1243,10 @@ static Value *takeLog2(IRBuilderBase &Builder, Value *Op, unsigned Depth,
12431243
Value *X, *Y;
12441244
if (match(Op, m_ZExt(m_Value(X))))
12451245
if (Value *LogX = takeLog2(Builder, X, Depth, AssumeNonZero, DoFold))
1246-
return IfFold([&]() { return Builder.CreateZExt(LogX, Op->getType()); });
1246+
return IfFold([&]() {
1247+
return Builder.CreateZExt(LogX, Op->getType(), /*Name*/ "",
1248+
/*IsNonNeg*/ true);
1249+
});
12471250

12481251
// log2(X << Y) -> log2(X) + Y
12491252
// FIXME: Require one use unless X is 1?

‎llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -408,7 +408,8 @@ Instruction *InstCombinerImpl::commonShiftTransforms(BinaryOperator &I) {
408408
// If the shift amount is a one-use `sext`, we can demote it to `zext`.
409409
Value *Y;
410410
if (match(Op1, m_OneUse(m_SExt(m_Value(Y))))) {
411-
Value *NewExt = Builder.CreateZExt(Y, Ty, Op1->getName());
411+
Value *NewExt =
412+
Builder.CreateZExt(Y, Ty, Op1->getName(), /*IsNonNeg*/ true);
412413
return BinaryOperator::Create(I.getOpcode(), Op0, NewExt);
413414
}
414415

@@ -1331,7 +1332,10 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
13311332
"Big shift not simplified to zero?");
13321333
// lshr (zext iM X to iN), C --> zext (lshr X, C) to iN
13331334
Value *NewLShr = Builder.CreateLShr(X, ShAmtC);
1334-
return new ZExtInst(NewLShr, Ty);
1335+
auto *Zext = new ZExtInst(NewLShr, Ty);
1336+
if (ShAmtC)
1337+
Zext->setNonNeg();
1338+
return Zext;
13351339
}
13361340

13371341
if (match(Op0, m_SExt(m_Value(X)))) {
@@ -1349,7 +1353,9 @@ Instruction *InstCombinerImpl::visitLShr(BinaryOperator &I) {
13491353
// zeros? lshr (sext iM X to iN), N-1 --> zext (lshr X, M-1) to iN
13501354
if (ShAmtC == BitWidth - 1) {
13511355
Value *NewLShr = Builder.CreateLShr(X, SrcTyBitWidth - 1);
1352-
return new ZExtInst(NewLShr, Ty);
1356+
auto *Zext = new ZExtInst(NewLShr, Ty);
1357+
Zext->setNonNeg();
1358+
return Zext;
13531359
}
13541360

13551361
// lshr (sext iM X to iN), N-M --> zext (ashr X, min(N-M, M-1)) to iN

‎llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -481,6 +481,8 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
481481
DemandedMask.getActiveBits() <= SrcBitWidth) {
482482
// Convert to ZExt cast.
483483
CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
484+
if (InputKnown.isNonNegative())
485+
NewCast->setNonNeg();
484486
return InsertNewInstWith(NewCast, I->getIterator());
485487
}
486488

‎llvm/test/Transforms/InstCombine/div-shift.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) {
3838
; rdar://11721329
3939
define i64 @t2(i64 %x, i32 %y) {
4040
; CHECK-LABEL: @t2(
41-
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[Y:%.*]] to i64
41+
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[Y:%.*]] to i64
4242
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[X:%.*]], [[TMP1]]
4343
; CHECK-NEXT: ret i64 [[TMP2]]
4444
;
@@ -52,7 +52,7 @@ define i64 @t2(i64 %x, i32 %y) {
5252
define i64 @t3(i64 %x, i32 %y) {
5353
; CHECK-LABEL: @t3(
5454
; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[Y:%.*]], 2
55-
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
55+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP1]] to i64
5656
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[X:%.*]], [[TMP2]]
5757
; CHECK-NEXT: ret i64 [[TMP3]]
5858
;

‎llvm/test/Transforms/InstCombine/load-cmp.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ define i1 @test4(i32 %X) {
122122

123123
define i1 @test4_i16(i16 %X) {
124124
; CHECK-LABEL: @test4_i16(
125-
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32
125+
; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i16 [[X:%.*]] to i32
126126
; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 933, [[TMP1]]
127127
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 1
128128
; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP3]], 0

‎llvm/test/Transforms/InstCombine/shift-by-signext.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66

77
define i32 @t0_shl(i32 %x, i8 %shamt) {
88
; CHECK-LABEL: @t0_shl(
9-
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
9+
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg i8 [[SHAMT:%.*]] to i32
1010
; CHECK-NEXT: [[R:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE1]]
1111
; CHECK-NEXT: ret i32 [[R]]
1212
;
@@ -16,7 +16,7 @@ define i32 @t0_shl(i32 %x, i8 %shamt) {
1616
}
1717
define i32 @t1_lshr(i32 %x, i8 %shamt) {
1818
; CHECK-LABEL: @t1_lshr(
19-
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
19+
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg i8 [[SHAMT:%.*]] to i32
2020
; CHECK-NEXT: [[R:%.*]] = lshr i32 [[X:%.*]], [[SHAMT_WIDE1]]
2121
; CHECK-NEXT: ret i32 [[R]]
2222
;
@@ -26,7 +26,7 @@ define i32 @t1_lshr(i32 %x, i8 %shamt) {
2626
}
2727
define i32 @t2_ashr(i32 %x, i8 %shamt) {
2828
; CHECK-LABEL: @t2_ashr(
29-
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
29+
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg i8 [[SHAMT:%.*]] to i32
3030
; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[SHAMT_WIDE1]]
3131
; CHECK-NEXT: ret i32 [[R]]
3232
;
@@ -37,7 +37,7 @@ define i32 @t2_ashr(i32 %x, i8 %shamt) {
3737

3838
define <2 x i32> @t3_vec_shl(<2 x i32> %x, <2 x i8> %shamt) {
3939
; CHECK-LABEL: @t3_vec_shl(
40-
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
40+
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg <2 x i8> [[SHAMT:%.*]] to <2 x i32>
4141
; CHECK-NEXT: [[R:%.*]] = shl <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
4242
; CHECK-NEXT: ret <2 x i32> [[R]]
4343
;
@@ -47,7 +47,7 @@ define <2 x i32> @t3_vec_shl(<2 x i32> %x, <2 x i8> %shamt) {
4747
}
4848
define <2 x i32> @t4_vec_lshr(<2 x i32> %x, <2 x i8> %shamt) {
4949
; CHECK-LABEL: @t4_vec_lshr(
50-
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
50+
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg <2 x i8> [[SHAMT:%.*]] to <2 x i32>
5151
; CHECK-NEXT: [[R:%.*]] = lshr <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
5252
; CHECK-NEXT: ret <2 x i32> [[R]]
5353
;
@@ -57,7 +57,7 @@ define <2 x i32> @t4_vec_lshr(<2 x i32> %x, <2 x i8> %shamt) {
5757
}
5858
define <2 x i32> @t5_vec_ashr(<2 x i32> %x, <2 x i8> %shamt) {
5959
; CHECK-LABEL: @t5_vec_ashr(
60-
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
60+
; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext nneg <2 x i8> [[SHAMT:%.*]] to <2 x i32>
6161
; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
6262
; CHECK-NEXT: ret <2 x i32> [[R]]
6363
;

‎llvm/test/Transforms/InstCombine/vector-udiv.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ define <4 x i32> @test_v4i32_shl_const_pow2(<4 x i32> %a0, <4 x i32> %a1) {
7575
define <4 x i32> @test_v4i32_zext_shl_splatconst_pow2(<4 x i32> %a0, <4 x i16> %a1) {
7676
; CHECK-LABEL: @test_v4i32_zext_shl_splatconst_pow2(
7777
; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i16> [[A1:%.*]], <i16 2, i16 2, i16 2, i16 2>
78-
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
78+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg <4 x i16> [[TMP1]] to <4 x i32>
7979
; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[A0:%.*]], [[TMP2]]
8080
; CHECK-NEXT: ret <4 x i32> [[TMP3]]
8181
;
@@ -88,7 +88,7 @@ define <4 x i32> @test_v4i32_zext_shl_splatconst_pow2(<4 x i32> %a0, <4 x i16> %
8888
define <4 x i32> @test_v4i32_zext_shl_const_pow2(<4 x i32> %a0, <4 x i16> %a1) {
8989
; CHECK-LABEL: @test_v4i32_zext_shl_const_pow2(
9090
; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i16> [[A1:%.*]], <i16 2, i16 3, i16 4, i16 5>
91-
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
91+
; CHECK-NEXT: [[TMP2:%.*]] = zext nneg <4 x i16> [[TMP1]] to <4 x i32>
9292
; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[A0:%.*]], [[TMP2]]
9393
; CHECK-NEXT: ret <4 x i32> [[TMP3]]
9494
;

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