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[AMDGPU] Clean up conversion of DPP instructions in AMDGPUDisassembler
Convert DPP instructions after all calls to tryDecodeInst, just like we do for all other instruction types. NFCI.
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+53
-74
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+53
-74
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llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 53 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -465,36 +465,25 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
465465
Res =
466466
tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696,
467467
MI, DecW, Address, CS);
468-
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
468+
if (Res)
469469
break;
470+
470471
Res =
471472
tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696,
472473
MI, DecW, Address, CS);
473-
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
474+
if (Res)
474475
break;
475476

476-
const auto convertVOPDPP = [&]() {
477-
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) {
478-
convertVOP3PDPPInst(MI);
479-
} else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) {
480-
convertVOPCDPPInst(MI); // Special VOP3 case
481-
} else {
482-
assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3);
483-
convertVOP3DPPInst(MI); // Regular VOP3 case
484-
}
485-
};
486477
Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696,
487478
MI, DecW, Address, CS);
488-
if (Res) {
489-
convertVOPDPP();
479+
if (Res)
490480
break;
491-
}
481+
492482
Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696,
493483
MI, DecW, Address, CS);
494-
if (Res) {
495-
convertVOPDPP();
484+
if (Res)
496485
break;
497-
}
486+
498487
Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS);
499488
if (Res)
500489
break;
@@ -515,47 +504,36 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
515504

516505
if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) {
517506
Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS);
518-
if (Res) {
519-
if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
520-
== -1)
521-
break;
522-
if (convertDPP8Inst(MI) == MCDisassembler::Success)
523-
break;
524-
}
507+
if (Res)
508+
break;
525509
}
526510

527511
Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS);
528-
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
512+
if (Res)
529513
break;
530514

531515
Res = tryDecodeInst(DecoderTableDPP8GFX1164,
532516
DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS);
533-
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
517+
if (Res)
534518
break;
535519

536520
Res = tryDecodeInst(DecoderTableDPP8GFX1264,
537521
DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS);
538-
if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
522+
if (Res)
539523
break;
540524

541525
Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS);
542526
if (Res) break;
543527

544528
Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664,
545529
MI, QW, Address, CS);
546-
if (Res) {
547-
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
548-
convertVOPCDPPInst(MI);
530+
if (Res)
549531
break;
550-
}
551532

552533
Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664,
553534
MI, QW, Address, CS);
554-
if (Res) {
555-
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
556-
convertVOPCDPPInst(MI);
535+
if (Res)
557536
break;
558-
}
559537

560538
if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) {
561539
Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS);
@@ -652,6 +630,22 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
652630
Address, CS);
653631
} while (false);
654632

633+
if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DPP)) {
634+
if (isMacDPP(MI))
635+
convertMacDPPInst(MI);
636+
637+
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P)
638+
convertVOP3PDPPInst(MI);
639+
else if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) ||
640+
AMDGPU::isVOPC64DPP(MI.getOpcode()))
641+
convertVOPCDPPInst(MI); // Special VOP3 case
642+
else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) !=
643+
-1)
644+
convertDPP8Inst(MI);
645+
else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3)
646+
convertVOP3DPPInst(MI); // Regular VOP3 case
647+
}
648+
655649
if (Res && AMDGPU::isMAC(MI.getOpcode())) {
656650
// Insert dummy unused src2_modifiers.
657651
insertNamedMCOperand(MI, MCOperand::createImm(0),
@@ -926,56 +920,41 @@ void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const {
926920
AMDGPU::OpName::src2_modifiers);
927921
}
928922

929-
// We must check FI == literal to reject not genuine dpp8 insts, and we must
930-
// first add optional MI operands to check FI
931923
DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
932924
unsigned Opc = MI.getOpcode();
933925

934-
if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) {
935-
convertVOP3PDPPInst(MI);
936-
} else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) ||
937-
AMDGPU::isVOPC64DPP(Opc)) {
938-
convertVOPCDPPInst(MI);
939-
} else {
940-
if (isMacDPP(MI))
941-
convertMacDPPInst(MI);
926+
int VDstInIdx =
927+
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in);
928+
if (VDstInIdx != -1)
929+
insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in);
942930

943-
int VDstInIdx =
944-
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in);
945-
if (VDstInIdx != -1)
946-
insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in);
931+
if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 ||
932+
MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12)
933+
insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2);
947934

948-
if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 ||
949-
MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12)
950-
insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2);
935+
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
936+
if (MI.getNumOperands() < DescNumOps &&
937+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
938+
convertTrue16OpSel(MI);
939+
auto Mods = collectVOPModifiers(MI);
940+
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel),
941+
AMDGPU::OpName::op_sel);
942+
} else {
943+
// Insert dummy unused src modifiers.
944+
if (MI.getNumOperands() < DescNumOps &&
945+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
946+
insertNamedMCOperand(MI, MCOperand::createImm(0),
947+
AMDGPU::OpName::src0_modifiers);
951948

952-
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
953949
if (MI.getNumOperands() < DescNumOps &&
954-
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
955-
convertTrue16OpSel(MI);
956-
auto Mods = collectVOPModifiers(MI);
957-
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel),
958-
AMDGPU::OpName::op_sel);
959-
} else {
960-
// Insert dummy unused src modifiers.
961-
if (MI.getNumOperands() < DescNumOps &&
962-
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
963-
insertNamedMCOperand(MI, MCOperand::createImm(0),
964-
AMDGPU::OpName::src0_modifiers);
965-
966-
if (MI.getNumOperands() < DescNumOps &&
967-
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
968-
insertNamedMCOperand(MI, MCOperand::createImm(0),
969-
AMDGPU::OpName::src1_modifiers);
970-
}
950+
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
951+
insertNamedMCOperand(MI, MCOperand::createImm(0),
952+
AMDGPU::OpName::src1_modifiers);
971953
}
972954
return MCDisassembler::Success;
973955
}
974956

975957
DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const {
976-
if (isMacDPP(MI))
977-
convertMacDPPInst(MI);
978-
979958
convertTrue16OpSel(MI);
980959

981960
int VDstInIdx =

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