@@ -1241,6 +1241,15 @@ let Predicates = [HasBMI, In64BitMode], Defs = [EFLAGS] in {
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defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64, "_EVEX">, EVEX;
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}
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+ let Predicates = [In64BitMode] in {
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+ defm BLSR32 : Bls<"blsr", MRM1r, MRM1m, Xi32, "_NF">, EVEX, EVEX_NF;
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+ defm BLSR64 : Bls<"blsr", MRM1r, MRM1m, Xi64, "_NF">, EVEX, EVEX_NF;
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+ defm BLSMSK32 : Bls<"blsmsk", MRM2r, MRM2m, Xi32, "_NF">, EVEX, EVEX_NF;
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+ defm BLSMSK64 : Bls<"blsmsk", MRM2r, MRM2m, Xi64, "_NF">, EVEX, EVEX_NF;
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+ defm BLSI32 : Bls<"blsi", MRM3r, MRM3m, Xi32, "_NF">, EVEX, EVEX_NF;
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+ defm BLSI64 : Bls<"blsi", MRM3r, MRM3m, Xi64, "_NF">, EVEX, EVEX_NF;
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+ }
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+
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let Predicates = [HasBMI] in {
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// FIXME(1): patterns for the load versions are not implemented
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// FIXME(2): By only matching `add_su` and `ineg_su` we may emit
@@ -1309,6 +1318,13 @@ let Predicates = [HasBMI2, HasEGPR, In64BitMode], Defs = [EFLAGS] in {
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defm BZHI64 : Bmi4VOp3<0xF5, "bzhi", Xi64, X86bzhi, WriteBZHI, "_EVEX">, EVEX;
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}
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+ let Predicates = [In64BitMode], Pattern = [(null_frag)] in {
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+ defm BEXTR32 : Bmi4VOp3<0xF7, "bextr", Xi32, X86bextr, WriteBEXTR, "_NF">, EVEX, EVEX_NF;
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+ defm BEXTR64 : Bmi4VOp3<0xF7, "bextr", Xi64, X86bextr, WriteBEXTR, "_NF">, EVEX, EVEX_NF;
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+ defm BZHI32 : Bmi4VOp3<0xF5, "bzhi", Xi32, X86bzhi, WriteBZHI, "_NF">, EVEX, EVEX_NF;
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+ defm BZHI64 : Bmi4VOp3<0xF5, "bzhi", Xi64, X86bzhi, WriteBZHI, "_NF">, EVEX, EVEX_NF;
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+ }
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+
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def CountTrailingOnes : SDNodeXForm<imm, [{
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// Count the trailing ones in the immediate.
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return getI8Imm(llvm::countr_one(N->getZExtValue()), SDLoc(N));
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