Remove swapped concat handling

Author: RKSimon

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -42675,6 +42675,9 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
     return SDValue();
   }
   case X86ISD::VPERMV3: {
+    MVT WideVT = VT.getDoubleNumVectorElementsVT();
+    bool CanConcat = VT.is128BitVector() ||
+                     (VT.is256BitVector() && Subtarget.useAVX512Regs());
     SmallVector<SDValue, 2> SrcOps;
     SmallVector<int, 32> Mask;
     if (getTargetShuffleMask(N, /*AllowSentinelZero=*/false, SrcOps, Mask)) {
@@ -42712,12 +42715,25 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
         return lowerShuffleWithPERMV(DL, VT, Mask, N.getOperand(2),
                                      N.getOperand(0), Subtarget, DAG);
       }
+      // Combine VPERMV3 to widened VPERMV if the two source operands can be
+      // freely concatenated, with a commuted shuffle mask.
+      if (CanConcat) {
+        if (SDValue ConcatSrc = combineConcatVectorOps(
+                DL, WideVT, {N.getOperand(2), N.getOperand(0)}, DAG,
+                Subtarget)) {
+          ShuffleVectorSDNode::commuteMask(Mask);
+          Mask.append(NumElts, SM_SentinelUndef);
+          SDValue Perm =
+              lowerShuffleWithPERMV(DL, WideVT, Mask, ConcatSrc,
+                                    DAG.getUNDEF(WideVT), Subtarget, DAG);
+          return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Perm,
+                             DAG.getVectorIdxConstant(0, DL));
+        }
+      }
     }
     // Combine VPERMV3 to widened VPERMV if the two source operands can be
     // freely concatenated.
-    MVT WideVT = VT.getDoubleNumVectorElementsVT();
-    if (VT.is128BitVector() ||
-        (VT.is256BitVector() && Subtarget.useAVX512Regs())) {
+    if (CanConcat) {
       SDValue Ops[] = {N.getOperand(0), N.getOperand(2)};
       if (SDValue ConcatSrc =
               combineConcatVectorOps(DL, WideVT, Ops, DAG, Subtarget)) {
@@ -42727,22 +42743,6 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
         return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Perm,
                            DAG.getVectorIdxConstant(0, DL));
       }
-      // See if we can concatenate the commuted operands (and then cheaply
-      // shuffle them, for constant shuffle masks this should fold away).
-      SDValue SwapOps[] = {N.getOperand(2), N.getOperand(0)};
-      if (SDValue ConcatSrc =
-              combineConcatVectorOps(DL, WideVT, SwapOps, DAG, Subtarget)) {
-        SmallVector<int, 16> SwapMask(WideVT.getVectorNumElements());
-        std::iota(SwapMask.begin(), SwapMask.begin() + NumElts, NumElts);
-        std::iota(SwapMask.begin() + NumElts, SwapMask.end(), 0);
-        SDValue Swap = DAG.getVectorShuffle(WideVT, DL, ConcatSrc,
-                                            DAG.getUNDEF(WideVT), SwapMask);
-        SDValue Mask = widenSubVector(N.getOperand(1), false, Subtarget, DAG,
-                                      DL, WideVT.getSizeInBits());
-        SDValue Perm = DAG.getNode(X86ISD::VPERMV, DL, WideVT, Mask, Swap);
-        return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Perm,
-                           DAG.getVectorIdxConstant(0, DL));
-      }
     }
     return SDValue();
   }

llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vl.ll

@@ -29,21 +29,15 @@ define <4 x double> @concat_vpermv3_ops_vpermv_v4f64(ptr %p0, <4 x i64> %m) {
 define <4 x double> @concat_vpermv3_ops_vpermv_swap_v4f64(ptr %p0, <4 x i64> %m) {
 ; X86-LABEL: concat_vpermv3_ops_vpermv_swap_v4f64:
 ; X86:       # %bb.0:
-; X86-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    vmovupd (%eax), %zmm1
-; X86-NEXT:    vshuff64x2 {{.*#+}} zmm1 = zmm1[4,5,6,7,0,1,2,3]
-; X86-NEXT:    vpermpd %zmm1, %zmm0, %zmm0
-; X86-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
+; X86-NEXT:    vmovapd 32(%eax), %ymm1
+; X86-NEXT:    vpermi2pd (%eax), %ymm1, %ymm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: concat_vpermv3_ops_vpermv_swap_v4f64:
 ; X64:       # %bb.0:
-; X64-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
-; X64-NEXT:    vmovupd (%rdi), %zmm1
-; X64-NEXT:    vshuff64x2 {{.*#+}} zmm1 = zmm1[4,5,6,7,0,1,2,3]
-; X64-NEXT:    vpermpd %zmm1, %zmm0, %zmm0
-; X64-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
+; X64-NEXT:    vmovapd 32(%rdi), %ymm1
+; X64-NEXT:    vpermi2pd (%rdi), %ymm1, %ymm0
 ; X64-NEXT:    retq
   %p1 = getelementptr inbounds nuw i8, ptr %p0, i64 32
   %lo = load <4 x double>, ptr %p1, align 32