Skip to content

Commit 0858c90

Browse files
RKSimonRKSimon
committed
[X86] Add missing register qualifier to the VBLENDVPD/VBLENDVPS/VPBLENDVB instruction names
Matches the SSE variants (which has a 0 qualifier to indicate the xmm0 explicit dependency)
1 parent a924da6 commit 0858c90

File tree

5 files changed

+42
-42
lines changed

5 files changed

+42
-42
lines changed

‎llvm/lib/Target/X86/X86FastISel.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2230,7 +2230,7 @@ bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) {
22302230
unsigned CmpOpcode =
22312231
(RetVT == MVT::f32) ? X86::VCMPSSrri : X86::VCMPSDrri;
22322232
unsigned BlendOpcode =
2233-
(RetVT == MVT::f32) ? X86::VBLENDVPSrr : X86::VBLENDVPDrr;
2233+
(RetVT == MVT::f32) ? X86::VBLENDVPSrrr : X86::VBLENDVPDrrr;
22342234

22352235
Register CmpReg = fastEmitInst_rri(CmpOpcode, RC, CmpLHSReg, CmpRHSReg,
22362236
CC);

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -6266,27 +6266,27 @@ multiclass SS41I_quaternary_avx<bits<8> opc, string OpcodeStr, RegisterClass RC,
62666266
X86MemOperand x86memop, ValueType VT,
62676267
PatFrag mem_frag, SDNode OpNode,
62686268
X86FoldableSchedWrite sched> {
6269-
def rr : Ii8Reg<opc, MRMSrcReg, (outs RC:$dst),
6270-
(ins RC:$src1, RC:$src2, RC:$src3),
6271-
!strconcat(OpcodeStr,
6272-
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6273-
[(set RC:$dst, (VT (OpNode RC:$src3, RC:$src2, RC:$src1)))],
6274-
SSEPackedInt>, TA, PD, VEX, VVVV,
6275-
Sched<[sched]>;
6269+
def rrr : Ii8Reg<opc, MRMSrcReg, (outs RC:$dst),
6270+
(ins RC:$src1, RC:$src2, RC:$src3),
6271+
!strconcat(OpcodeStr,
6272+
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6273+
[(set RC:$dst, (VT (OpNode RC:$src3, RC:$src2, RC:$src1)))],
6274+
SSEPackedInt>, TA, PD, VEX, VVVV,
6275+
Sched<[sched]>;
62766276

6277-
def rm : Ii8Reg<opc, MRMSrcMem, (outs RC:$dst),
6278-
(ins RC:$src1, x86memop:$src2, RC:$src3),
6279-
!strconcat(OpcodeStr,
6280-
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6281-
[(set RC:$dst,
6282-
(OpNode RC:$src3, (mem_frag addr:$src2),
6283-
RC:$src1))], SSEPackedInt>, TA, PD, VEX, VVVV,
6284-
Sched<[sched.Folded, sched.ReadAfterFold,
6285-
// x86memop:$src2
6286-
ReadDefault, ReadDefault, ReadDefault, ReadDefault,
6287-
ReadDefault,
6288-
// RC::$src3
6289-
sched.ReadAfterFold]>;
6277+
def rmr : Ii8Reg<opc, MRMSrcMem, (outs RC:$dst),
6278+
(ins RC:$src1, x86memop:$src2, RC:$src3),
6279+
!strconcat(OpcodeStr,
6280+
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6281+
[(set RC:$dst,
6282+
(OpNode RC:$src3, (mem_frag addr:$src2),
6283+
RC:$src1))], SSEPackedInt>, TA, PD, VEX, VVVV,
6284+
Sched<[sched.Folded, sched.ReadAfterFold,
6285+
// x86memop:$src2
6286+
ReadDefault, ReadDefault, ReadDefault, ReadDefault,
6287+
ReadDefault,
6288+
// RC::$src3
6289+
sched.ReadAfterFold]>;
62906290
}
62916291

62926292
let Predicates = [HasAVX] in {
@@ -6320,16 +6320,16 @@ defm VPBLENDVBY : SS41I_quaternary_avx<0x4C, "vpblendvb", VR256, i256mem,
63206320
let Predicates = [HasAVX] in {
63216321
def : Pat<(v4i32 (X86Blendv (v4i32 VR128:$mask), (v4i32 VR128:$src1),
63226322
(v4i32 VR128:$src2))),
6323-
(VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6323+
(VBLENDVPSrrr VR128:$src2, VR128:$src1, VR128:$mask)>;
63246324
def : Pat<(v2i64 (X86Blendv (v2i64 VR128:$mask), (v2i64 VR128:$src1),
63256325
(v2i64 VR128:$src2))),
6326-
(VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6326+
(VBLENDVPDrrr VR128:$src2, VR128:$src1, VR128:$mask)>;
63276327
def : Pat<(v8i32 (X86Blendv (v8i32 VR256:$mask), (v8i32 VR256:$src1),
63286328
(v8i32 VR256:$src2))),
6329-
(VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6329+
(VBLENDVPSYrrr VR256:$src2, VR256:$src1, VR256:$mask)>;
63306330
def : Pat<(v4i64 (X86Blendv (v4i64 VR256:$mask), (v4i64 VR256:$src1),
63316331
(v4i64 VR256:$src2))),
6332-
(VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6332+
(VBLENDVPDYrrr VR256:$src2, VR256:$src1, VR256:$mask)>;
63336333
}
63346334

63356335
// Prefer a movss or movsd over a blendps when optimizing for size. these were

‎llvm/lib/Target/X86/X86SchedAlderlakeP.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2158,16 +2158,16 @@ def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
21582158
let Latency = 9;
21592159
let NumMicroOps = 4;
21602160
}
2161-
def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
2162-
def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
2161+
def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rmr$")>;
2162+
def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrmr)>;
21632163

21642164
def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00_01_05]> {
21652165
let ReleaseAtCycles = [3];
21662166
let Latency = 3;
21672167
let NumMicroOps = 3;
21682168
}
2169-
def : InstRW<[ADLPWriteResGroup245], (instregex "^VBLENDVP(D|S)rr$")>;
2170-
def : InstRW<[ADLPWriteResGroup245], (instrs VPBLENDVBrr)>;
2169+
def : InstRW<[ADLPWriteResGroup245], (instregex "^VBLENDVP(D|S)rrr$")>;
2170+
def : InstRW<[ADLPWriteResGroup245], (instrs VPBLENDVBrrr)>;
21712171

21722172
def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
21732173
let ReleaseAtCycles = [6, 7, 18];

‎llvm/lib/Target/X86/X86SchedSapphireRapids.td

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2673,25 +2673,25 @@ def SPRWriteResGroup259 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
26732673
let Latency = 10;
26742674
let NumMicroOps = 4;
26752675
}
2676-
def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)Yrm$")>;
2677-
def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBYrm)>;
2676+
def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)Yrmr$")>;
2677+
def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBYrmr)>;
26782678

26792679
def SPRWriteResGroup260 : SchedWriteRes<[SPRPort00_01_05]> {
26802680
let ReleaseAtCycles = [3];
26812681
let Latency = 3;
26822682
let NumMicroOps = 3;
26832683
}
2684-
def : InstRW<[SPRWriteResGroup260], (instregex "^VBLENDVP(S|DY)rr$",
2685-
"^VBLENDVP(D|SY)rr$",
2686-
"^VPBLENDVB(Y?)rr$")>;
2684+
def : InstRW<[SPRWriteResGroup260], (instregex "^VBLENDVP(S|DY)rrr$",
2685+
"^VBLENDVP(D|SY)rrr$",
2686+
"^VPBLENDVB(Y?)rrr$")>;
26872687

26882688
def SPRWriteResGroup261 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
26892689
let ReleaseAtCycles = [3, 1];
26902690
let Latency = 9;
26912691
let NumMicroOps = 4;
26922692
}
2693-
def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
2694-
def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
2693+
def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rmr$")>;
2694+
def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrmr)>;
26952695

26962696
def SPRWriteResGroup262 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
26972697
let Latency = 9;

‎llvm/test/TableGen/x86-fold-tables.inc

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2363,10 +2363,10 @@ static const X86FoldTableEntry Table2[] = {
23632363
{X86::VBLENDPDrri, X86::VBLENDPDrmi, 0},
23642364
{X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0},
23652365
{X86::VBLENDPSrri, X86::VBLENDPSrmi, 0},
2366-
{X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0},
2367-
{X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0},
2368-
{X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0},
2369-
{X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0},
2366+
{X86::VBLENDVPDYrrr, X86::VBLENDVPDYrmr, 0},
2367+
{X86::VBLENDVPDrrr, X86::VBLENDVPDrmr, 0},
2368+
{X86::VBLENDVPSYrrr, X86::VBLENDVPSYrmr, 0},
2369+
{X86::VBLENDVPSrrr, X86::VBLENDVPSrmr, 0},
23702370
{X86::VBROADCASTF32X2Z256rrkz, X86::VBROADCASTF32X2Z256rmkz, TB_NO_REVERSE},
23712371
{X86::VBROADCASTF32X2Zrrkz, X86::VBROADCASTF32X2Zrmkz, TB_NO_REVERSE},
23722372
{X86::VBROADCASTI32X2Z128rrkz, X86::VBROADCASTI32X2Z128rmkz, TB_NO_REVERSE},
@@ -3042,8 +3042,8 @@ static const X86FoldTableEntry Table2[] = {
30423042
{X86::VPBLENDMWZ128rr, X86::VPBLENDMWZ128rm, 0},
30433043
{X86::VPBLENDMWZ256rr, X86::VPBLENDMWZ256rm, 0},
30443044
{X86::VPBLENDMWZrr, X86::VPBLENDMWZrm, 0},
3045-
{X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0},
3046-
{X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0},
3045+
{X86::VPBLENDVBYrrr, X86::VPBLENDVBYrmr, 0},
3046+
{X86::VPBLENDVBrrr, X86::VPBLENDVBrmr, 0},
30473047
{X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0},
30483048
{X86::VPBLENDWrri, X86::VPBLENDWrmi, 0},
30493049
{X86::VPBROADCASTBZ128rrkz, X86::VPBROADCASTBZ128rmkz, TB_NO_REVERSE},

0 commit comments

Comments
 (0)