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zixuan-wuzixuan-wu
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[CSKY] Fix the testcase error due to the verifyInstructionPredicates
- Test cases for arch only has 16-bit instruction such as ck801/ck802 need compile with -mattr=+btst16 - Fix the GPR copy instruction with MOV16 for 16-bit only arch.
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8 files changed

+7
-265
lines changed

8 files changed

+7
-265
lines changed

‎llvm/lib/Target/CSKY/CSKYInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -518,7 +518,7 @@ void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
518518

519519
unsigned Opcode = 0;
520520
if (CSKY::GPRRegClass.contains(DestReg, SrcReg))
521-
Opcode = CSKY::MOV32;
521+
Opcode = STI.hasE2() ? CSKY::MOV32 : CSKY::MOV16;
522522
else if (v2sf && CSKY::sFPR32RegClass.contains(DestReg, SrcReg))
523523
Opcode = CSKY::FMOV_S;
524524
else if (v3sf && CSKY::FPR32RegClass.contains(DestReg, SrcReg))

‎llvm/test/CodeGen/CSKY/base-i.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 -mattr=+2e3 < %s -mtriple=csky | FileCheck %s
3-
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
3+
; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+btst16 < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
44

55
define i32 @addRR(i32 %x, i32 %y) {
66
; CHECK-LABEL: addRR:

‎llvm/test/CodeGen/CSKY/br.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
3-
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
3+
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16 | FileCheck %s --check-prefix=GENERIC
44

55
;EQ
66
define i32 @brRR_eq(i32 %x, i32 %y) {

‎llvm/test/CodeGen/CSKY/call-16bit.ll

Lines changed: 0 additions & 134 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s
3-
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=small | FileCheck %s --check-prefix=CHECK-PIC-SMALL
4-
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=large | FileCheck %s --check-prefix=CHECK-PIC-LARGE
53

64
@p_fun = global void (i32, i32)* @bar, align 8
75

@@ -29,69 +27,6 @@ define void @foo(i32 %a, i32* %ptr){
2927
; CHECK-NEXT: .LCPI0_0:
3028
; CHECK-NEXT: .long bar
3129
;
32-
; CHECK-PIC-SMALL-LABEL: foo:
33-
; CHECK-PIC-SMALL: # %bb.0: # %entry
34-
; CHECK-PIC-SMALL-NEXT: subi16 sp, sp, 8
35-
; CHECK-PIC-SMALL-NEXT: .cfi_def_cfa_offset 8
36-
; CHECK-PIC-SMALL-NEXT: st32.w rgb, (sp, 4) # 4-byte Folded Spill
37-
; CHECK-PIC-SMALL-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
38-
; CHECK-PIC-SMALL-NEXT: .cfi_offset rgb, -4
39-
; CHECK-PIC-SMALL-NEXT: .cfi_offset lr, -8
40-
; CHECK-PIC-SMALL-NEXT: subi16 sp, sp, 4
41-
; CHECK-PIC-SMALL-NEXT: .cfi_def_cfa_offset 12
42-
; CHECK-PIC-SMALL-NEXT: lrw32 rgb, [.LCPI0_0]
43-
; CHECK-PIC-SMALL-NEXT: mov32 a2, rgb
44-
; CHECK-PIC-SMALL-NEXT: ld16.w a1, (a1, 0)
45-
; CHECK-PIC-SMALL-NEXT: lrw32 a3, [.LCPI0_1]
46-
; CHECK-PIC-SMALL-NEXT: addu16 a2, a2, a3
47-
; CHECK-PIC-SMALL-NEXT: ld16.w a2, (a2, 0)
48-
; CHECK-PIC-SMALL-NEXT: jsr16 a2
49-
; CHECK-PIC-SMALL-NEXT: addi16 sp, sp, 4
50-
; CHECK-PIC-SMALL-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
51-
; CHECK-PIC-SMALL-NEXT: ld32.w rgb, (sp, 4) # 4-byte Folded Reload
52-
; CHECK-PIC-SMALL-NEXT: addi16 sp, sp, 8
53-
; CHECK-PIC-SMALL-NEXT: rts16
54-
; CHECK-PIC-SMALL-NEXT: .p2align 1
55-
; CHECK-PIC-SMALL-NEXT: # %bb.1:
56-
; CHECK-PIC-SMALL-NEXT: .p2align 2
57-
; CHECK-PIC-SMALL-NEXT: .LCPI0_0:
58-
; CHECK-PIC-SMALL-NEXT: .long _GLOBAL_OFFSET_TABLE_
59-
; CHECK-PIC-SMALL-NEXT: .LCPI0_1:
60-
; CHECK-PIC-SMALL-NEXT: .long bar@PLT
61-
;
62-
; CHECK-PIC-LARGE-LABEL: foo:
63-
; CHECK-PIC-LARGE: # %bb.0: # %entry
64-
; CHECK-PIC-LARGE-NEXT: subi16 sp, sp, 8
65-
; CHECK-PIC-LARGE-NEXT: .cfi_def_cfa_offset 8
66-
; CHECK-PIC-LARGE-NEXT: st32.w rgb, (sp, 4) # 4-byte Folded Spill
67-
; CHECK-PIC-LARGE-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
68-
; CHECK-PIC-LARGE-NEXT: .cfi_offset rgb, -4
69-
; CHECK-PIC-LARGE-NEXT: .cfi_offset lr, -8
70-
; CHECK-PIC-LARGE-NEXT: subi16 sp, sp, 4
71-
; CHECK-PIC-LARGE-NEXT: .cfi_def_cfa_offset 12
72-
; CHECK-PIC-LARGE-NEXT: lrw32 rgb, [.LCPI0_0]
73-
; CHECK-PIC-LARGE-NEXT: mov32 a2, rgb
74-
; CHECK-PIC-LARGE-NEXT: ld16.w a1, (a1, 0)
75-
; CHECK-PIC-LARGE-NEXT: lrw32 a3, [.LCPI0_1]
76-
; CHECK-PIC-LARGE-NEXT: addu16 a2, a2, a3
77-
; CHECK-PIC-LARGE-NEXT: ld16.w a2, (a2, 0)
78-
; CHECK-PIC-LARGE-NEXT: jsr16 a2
79-
; CHECK-PIC-LARGE-NEXT: addi16 sp, sp, 4
80-
; CHECK-PIC-LARGE-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
81-
; CHECK-PIC-LARGE-NEXT: ld32.w rgb, (sp, 4) # 4-byte Folded Reload
82-
; CHECK-PIC-LARGE-NEXT: addi16 sp, sp, 8
83-
; CHECK-PIC-LARGE-NEXT: rts16
84-
; CHECK-PIC-LARGE-NEXT: .p2align 1
85-
; CHECK-PIC-LARGE-NEXT: # %bb.1:
86-
; CHECK-PIC-LARGE-NEXT: .p2align 2
87-
; CHECK-PIC-LARGE-NEXT: .LCPI0_0:
88-
; CHECK-PIC-LARGE-NEXT: .long _GLOBAL_OFFSET_TABLE_
89-
; CHECK-PIC-LARGE-NEXT: .LCPI0_1:
90-
; CHECK-PIC-LARGE-NEXT: .long bar@PLT
91-
; CHECK-PIC-LABEL: foo:
92-
; CHECK-PIC: # %bb.0: # %entry
93-
; CHECK-PIC-NEXT: ld32.w a1, a1, 0
94-
; CHECK-PIC-NEXT: br32 bar
9530
entry:
9631
%0 = load i32, i32* %ptr
9732
tail call void (i32, i32) @bar(i32 %a, i32 %0)
@@ -121,75 +56,6 @@ define void @foo_indirect(i32 %a, i32* %ptr) {
12156
; CHECK-NEXT: .LCPI1_0:
12257
; CHECK-NEXT: .long p_fun
12358
;
124-
; CHECK-PIC-SMALL-LABEL: foo_indirect:
125-
; CHECK-PIC-SMALL: # %bb.0: # %entry
126-
; CHECK-PIC-SMALL-NEXT: subi16 sp, sp, 8
127-
; CHECK-PIC-SMALL-NEXT: .cfi_def_cfa_offset 8
128-
; CHECK-PIC-SMALL-NEXT: st32.w rgb, (sp, 4) # 4-byte Folded Spill
129-
; CHECK-PIC-SMALL-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
130-
; CHECK-PIC-SMALL-NEXT: .cfi_offset rgb, -4
131-
; CHECK-PIC-SMALL-NEXT: .cfi_offset lr, -8
132-
; CHECK-PIC-SMALL-NEXT: subi16 sp, sp, 4
133-
; CHECK-PIC-SMALL-NEXT: .cfi_def_cfa_offset 12
134-
; CHECK-PIC-SMALL-NEXT: lrw32 rgb, [.LCPI1_0]
135-
; CHECK-PIC-SMALL-NEXT: mov32 a2, rgb
136-
; CHECK-PIC-SMALL-NEXT: lrw32 a3, [.LCPI1_1]
137-
; CHECK-PIC-SMALL-NEXT: addu16 a2, a2, a3
138-
; CHECK-PIC-SMALL-NEXT: ld16.w a2, (a2, 0)
139-
; CHECK-PIC-SMALL-NEXT: ld16.w a2, (a2, 0)
140-
; CHECK-PIC-SMALL-NEXT: ld16.w a1, (a1, 0)
141-
; CHECK-PIC-SMALL-NEXT: jsr16 a2
142-
; CHECK-PIC-SMALL-NEXT: addi16 sp, sp, 4
143-
; CHECK-PIC-SMALL-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
144-
; CHECK-PIC-SMALL-NEXT: ld32.w rgb, (sp, 4) # 4-byte Folded Reload
145-
; CHECK-PIC-SMALL-NEXT: addi16 sp, sp, 8
146-
; CHECK-PIC-SMALL-NEXT: rts16
147-
; CHECK-PIC-SMALL-NEXT: .p2align 1
148-
; CHECK-PIC-SMALL-NEXT: # %bb.1:
149-
; CHECK-PIC-SMALL-NEXT: .p2align 2
150-
; CHECK-PIC-SMALL-NEXT: .LCPI1_0:
151-
; CHECK-PIC-SMALL-NEXT: .long _GLOBAL_OFFSET_TABLE_
152-
; CHECK-PIC-SMALL-NEXT: .LCPI1_1:
153-
; CHECK-PIC-SMALL-NEXT: .long p_fun@GOT
154-
;
155-
; CHECK-PIC-LARGE-LABEL: foo_indirect:
156-
; CHECK-PIC-LARGE: # %bb.0: # %entry
157-
; CHECK-PIC-LARGE-NEXT: subi16 sp, sp, 8
158-
; CHECK-PIC-LARGE-NEXT: .cfi_def_cfa_offset 8
159-
; CHECK-PIC-LARGE-NEXT: st32.w rgb, (sp, 4) # 4-byte Folded Spill
160-
; CHECK-PIC-LARGE-NEXT: st32.w lr, (sp, 0) # 4-byte Folded Spill
161-
; CHECK-PIC-LARGE-NEXT: .cfi_offset rgb, -4
162-
; CHECK-PIC-LARGE-NEXT: .cfi_offset lr, -8
163-
; CHECK-PIC-LARGE-NEXT: subi16 sp, sp, 4
164-
; CHECK-PIC-LARGE-NEXT: .cfi_def_cfa_offset 12
165-
; CHECK-PIC-LARGE-NEXT: lrw32 rgb, [.LCPI1_0]
166-
; CHECK-PIC-LARGE-NEXT: mov32 a2, rgb
167-
; CHECK-PIC-LARGE-NEXT: lrw32 a3, [.LCPI1_1]
168-
; CHECK-PIC-LARGE-NEXT: addu16 a2, a2, a3
169-
; CHECK-PIC-LARGE-NEXT: ld16.w a2, (a2, 0)
170-
; CHECK-PIC-LARGE-NEXT: ld16.w a2, (a2, 0)
171-
; CHECK-PIC-LARGE-NEXT: ld16.w a1, (a1, 0)
172-
; CHECK-PIC-LARGE-NEXT: jsr16 a2
173-
; CHECK-PIC-LARGE-NEXT: addi16 sp, sp, 4
174-
; CHECK-PIC-LARGE-NEXT: ld32.w lr, (sp, 0) # 4-byte Folded Reload
175-
; CHECK-PIC-LARGE-NEXT: ld32.w rgb, (sp, 4) # 4-byte Folded Reload
176-
; CHECK-PIC-LARGE-NEXT: addi16 sp, sp, 8
177-
; CHECK-PIC-LARGE-NEXT: rts16
178-
; CHECK-PIC-LARGE-NEXT: .p2align 1
179-
; CHECK-PIC-LARGE-NEXT: # %bb.1:
180-
; CHECK-PIC-LARGE-NEXT: .p2align 2
181-
; CHECK-PIC-LARGE-NEXT: .LCPI1_0:
182-
; CHECK-PIC-LARGE-NEXT: .long _GLOBAL_OFFSET_TABLE_
183-
; CHECK-PIC-LARGE-NEXT: .LCPI1_1:
184-
; CHECK-PIC-LARGE-NEXT: .long p_fun@GOT
185-
; CHECK-PIC-LABEL: foo_indirect:
186-
; CHECK-PIC: # %bb.0: # %entry
187-
; CHECK-PIC-NEXT: movi32 a2, p_fun
188-
; CHECK-PIC-NEXT: movih32 a3, p_fun
189-
; CHECK-PIC-NEXT: or32 a2, a3, a2
190-
; CHECK-PIC-NEXT: ld32.w a2, a2, 0
191-
; CHECK-PIC-NEXT: ld32.w a1, a1, 0
192-
; CHECK-PIC-NEXT: jmp32 a2
19359
entry:
19460
%0 = load void (i32, i32)*, void (i32, i32)** @p_fun, align 8
19561
%1 = load i32, i32* %ptr

‎llvm/test/CodeGen/CSKY/cmp-i.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
3-
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
3+
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16 | FileCheck %s --check-prefix=GENERIC
44

55
;eq
66
define i1 @icmpRR_eq(i32 %x, i32 %y) {

‎llvm/test/CodeGen/CSKY/fpu/select.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s
33
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv3_sf,+fpuv3_df -float-abi=hard | FileCheck %s --check-prefix=CHECK-DF3
4-
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC
4+
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC
55

66
define float @selectRR_eq_float(i1 %x, float %n, float %m) {
77
; CHECK-LABEL: selectRR_eq_float:

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