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jwanggit86jwanggit86
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Update tests after merging from main.
1 parent b3c81f9 commit 09012f4

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+309
-316
lines changed

‎llvm/test/CodeGen/AMDGPU/addrspacecast.ll

Lines changed: 20 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -63,16 +63,23 @@ define void @use_group_to_flat_addrspacecast_func(ptr addrspace(3) %ptr) #0 {
6363

6464
; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast:
6565

66-
; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[6:7], 0x0{{$}}
67-
; GFX9-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x0{{$}}
68-
; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], [[APERTURE]]
69-
; HSA-DAG: s_mov_b64 s[{{[0-9]+}}:[[RSRCHI:[0-9]+]]], s[2:3]
70-
; HSA-DAG: s_mov_b64 s[[[BASELO:[0-9]+]]:[[BASEHI:[0-9]+]]], s[0:1]
71-
; SI-DAG: s_add_u32 s[[BASELO]], s[[BASELO]], s9
72-
; GFX9-DAG: s_add_u32 s[[BASELO]], s[[BASELO]], s7
73-
; HSA-DAG: s_addc_u32 s[[BASEHI]], s[[BASEHI]], 0
74-
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
75-
; HSA: buffer_store_dword [[K]], [[PTR]], s[[[BASELO]]:[[RSRCHI]]], 0 offen
66+
; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
67+
; CI-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}}
68+
69+
; CI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
70+
; CI-DAG: s_cmp_lg_u32 [[PTR]], -1
71+
; CI-DAG: s_cselect_b32 s[[HI:[0-9]+]], [[APERTURE]], 0
72+
; CI-DAG: s_cselect_b32 s[[LO:[0-9]+]], [[PTR]], 0
73+
74+
; GFX9-DAG: s_load_dword [[PTR:s[0-9]+]], s[4:5], 0x0{{$}}
75+
; GFX9-DAG: s_mov_b64 s[{{[0-9]+}}:[[HIBASE:[0-9]+]]], src_private_base
76+
77+
; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
78+
; GFX9: s_cmp_lg_u32 [[PTR]], -1
79+
; GFX9: s_cselect_b32 s[[LO:[0-9]+]], s[[HIBASE]], 0
80+
; GFX9: s_cselect_b32 s[[HI:[0-9]+]], [[PTR]], 0
81+
82+
; HSA: flat_store_dword v[[[LO]]:[[HI]]], [[K]]
7683

7784
; HSA: .amdhsa_user_sgpr_private_segment_buffer 1
7885
; HSA: .amdhsa_user_sgpr_dispatch_ptr 0
@@ -252,11 +259,8 @@ define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 {
252259

253260
; FIXME: Shouldn't need to enable queue ptr
254261
; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast:
255-
; HSA-DAG: s_mov_b64 s[{{[0-9]+}}:[[RSRCHI:[0-9]+]]], s[2:3]
256-
; HSA-DAG: s_mov_b64 s[[[BASELO:[0-9]+]]:[[BASEHI:[0-9]+]]], s[0:1]
257-
; CI-DAG: s_add_u32 s[[BASELO]], s[[BASELO]], s7
258-
; GFX9-DAG: s_add_u32 s[[BASELO]], s[[BASELO]], s5
259-
; HSA-DAG: s_addc_u32 s[[BASEHI]], s[[BASEHI]], 0
262+
; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
263+
; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
260264
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
261265
; HSA: flat_store_dword v[[[LO]]:[[HI]]], v[[K]]
262266
define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 {
@@ -277,12 +281,7 @@ define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 {
277281

278282
; HSA-LABEL: {{^}}cast_neg1_private_to_flat_addrspacecast:
279283

280-
; HSA-DAG: s_mov_b64 s[{{[0-9]+}}:[[RSRCHI:[0-9]+]]], s[2:3]
281-
; HSA-DAG: s_mov_b64 s[[[BASELO:[0-9]+]]:[[BASEHI:[0-9]+]]], s[0:1]
282-
; CI-DAG: s_add_u32 s[[BASELO]], s[[BASELO]], s7
283-
; GFX9-DAG: s_add_u32 s[[BASELO]], s[[BASELO]], s5
284-
; HSA-DAG: s_addc_u32 s[[BASEHI]], s[[BASEHI]], 0
285-
; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
284+
; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
286285
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
287286
; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
288287
; HSA: {{flat|global}}_store_dword v[[[LO]]:[[HI]]], v[[K]]

‎llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -393,12 +393,11 @@ define amdgpu_kernel void @select_add_lhs_const_i16(i1 %cond) {
393393
; GCN-LABEL: select_add_lhs_const_i16:
394394
; GCN: ; %bb.0:
395395
; GCN-NEXT: s_load_dword s0, s[6:7], 0x0
396-
; GCN-NEXT: v_mov_b32_e32 v0, 0x83
397-
; GCN-NEXT: v_mov_b32_e32 v1, 0x80
398396
; GCN-NEXT: s_waitcnt lgkmcnt(0)
399397
; GCN-NEXT: s_bitcmp1_b32 s0, 0
400-
; GCN-NEXT: s_cselect_b64 vcc, -1, 0
401-
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
398+
; GCN-NEXT: s_movk_i32 s0, 0x80
399+
; GCN-NEXT: s_cselect_b32 s0, s0, 0x83
400+
; GCN-NEXT: v_mov_b32_e32 v0, s0
402401
; GCN-NEXT: flat_store_short v[0:1], v0
403402
; GCN-NEXT: s_endpgm
404403
%select = select i1 %cond, i16 5, i16 8

‎llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -443,7 +443,8 @@ define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %p
443443
;
444444
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_private_to_flat_addrspacecast
445445
; ATTRIBUTOR_HSA-SAME: (ptr addrspace(5) [[PTR:%.*]]) #[[ATTR13:[0-9]+]] {
446-
; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, ptr addrspace(5) [[PTR]], align 4
446+
; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(5) [[PTR]] to ptr
447+
; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4
447448
; ATTRIBUTOR_HSA-NEXT: ret void
448449
;
449450
%stof = addrspacecast ptr addrspace(5) %ptr to ptr
@@ -485,7 +486,8 @@ define amdgpu_kernel void @use_global_to_flat_addrspacecast(ptr addrspace(1) %pt
485486
;
486487
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_global_to_flat_addrspacecast
487488
; ATTRIBUTOR_HSA-SAME: (ptr addrspace(1) [[PTR:%.*]]) #[[ATTR1]] {
488-
; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, ptr addrspace(1) [[PTR]], align 4
489+
; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr
490+
; ATTRIBUTOR_HSA-NEXT: store volatile i32 0, ptr [[STOF]], align 4
489491
; ATTRIBUTOR_HSA-NEXT: ret void
490492
;
491493
%stof = addrspacecast ptr addrspace(1) %ptr to ptr
@@ -502,7 +504,8 @@ define amdgpu_kernel void @use_constant_to_flat_addrspacecast(ptr addrspace(4) %
502504
;
503505
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@use_constant_to_flat_addrspacecast
504506
; ATTRIBUTOR_HSA-SAME: (ptr addrspace(4) [[PTR:%.*]]) #[[ATTR1]] {
505-
; ATTRIBUTOR_HSA-NEXT: [[LD:%.*]] = load volatile i32, ptr addrspace(4) [[PTR]], align 4
507+
; ATTRIBUTOR_HSA-NEXT: [[STOF:%.*]] = addrspacecast ptr addrspace(4) [[PTR]] to ptr
508+
; ATTRIBUTOR_HSA-NEXT: [[LD:%.*]] = load volatile i32, ptr [[STOF]], align 4
506509
; ATTRIBUTOR_HSA-NEXT: ret void
507510
;
508511
%stof = addrspacecast ptr addrspace(4) %ptr to ptr

‎llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -33,9 +33,9 @@ define void @indirect_use_vcc() #1 {
3333
}
3434

3535
; GCN-LABEL: {{^}}indirect_2level_use_vcc_kernel:
36-
; CI: ; NumSgprs: 38
37-
; VI-NOBUG: ; NumSgprs: 40
38-
; VI-BUG: ; NumSgprs: 96
36+
; CI: ; TotalNumSgprs: 38
37+
; VI-NOBUG: ; TotalNumSgprs: 40
38+
; VI-BUG: ; TotalNumSgprs: 96
3939
; GCN: ; NumVgprs: 41
4040
define amdgpu_kernel void @indirect_2level_use_vcc_kernel(ptr addrspace(1) %out) #0 {
4141
call void @indirect_use_vcc()
@@ -121,9 +121,9 @@ define void @indirect_use_80_sgpr() #1 {
121121
}
122122

123123
; GCN-LABEL: {{^}}indirect_2_level_use_80_sgpr:
124-
; CI: ; NumSgprs: 84
125-
; VI-NOBUG: ; NumSgprs: 86
126-
; VI-BUG: ; NumSgprs: 96
124+
; CI: ; TotalNumSgprs: 84
125+
; VI-NOBUG: ; TotalNumSgprs: 86
126+
; VI-BUG: ; TotalNumSgprs: 96
127127
define amdgpu_kernel void @indirect_2_level_use_80_sgpr() #0 {
128128
call void @indirect_use_80_sgpr()
129129
ret void

‎llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -25,11 +25,11 @@
2525
; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
2626
; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
2727

28-
; CI: ; NumSgprs: 8
29-
; VI-NOXNACK: ; NumSgprs: 8
30-
; VI-XNACK: ; NumSgprs: 12
31-
; GFX9-ARCH-FLAT: ; NumSgprs: 14
32-
; GFX10-ARCH-FLAT: ; NumSgprs: 8
28+
; CI: ; TotalNumSgprs: 8
29+
; VI-NOXNACK: ; TotalNumSgprs: 8
30+
; VI-XNACK: ; TotalNumSgprs: 12
31+
; GFX9-ARCH-FLAT: ; TotalNumSgprs: 14
32+
; GFX10-ARCH-FLAT: ; TotalNumSgprs: 8
3333
define amdgpu_kernel void @no_vcc_no_flat() {
3434
entry:
3535
call void asm sideeffect "", "~{s7}"()
@@ -42,11 +42,11 @@ entry:
4242
; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
4343
; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
4444

45-
; CI: ; NumSgprs: 10
46-
; VI-NOXNACK: ; NumSgprs: 10
47-
; VI-XNACK: ; NumSgprs: 12
48-
; GFX9-ARCH-FLAT: ; NumSgprs: 14
49-
; GFX10-ARCH-FLAT: ; NumSgprs: 10
45+
; CI: ; TotalNumSgprs: 10
46+
; VI-NOXNACK: ; TotalNumSgprs: 10
47+
; VI-XNACK: ; TotalNumSgprs: 12
48+
; GFX9-ARCH-FLAT: ; TotalNumSgprs: 14
49+
; GFX10-ARCH-FLAT: ; TotalNumSgprs: 10
5050
define amdgpu_kernel void @vcc_no_flat() {
5151
entry:
5252
call void asm sideeffect "", "~{s7},~{vcc}"()
@@ -59,11 +59,11 @@ entry:
5959
; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
6060
; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
6161

62-
; CI: ; NumSgprs: 12
63-
; VI-NOXNACK: ; NumSgprs: 14
64-
; VI-XNACK: ; NumSgprs: 14
65-
; GFX9-ARCH-FLAT: ; NumSgprs: 14
66-
; GFX10-ARCH-FLAT: ; NumSgprs: 8
62+
; CI: ; TotalNumSgprs: 12
63+
; VI-NOXNACK: ; TotalNumSgprs: 14
64+
; VI-XNACK: ; TotalNumSgprs: 14
65+
; GFX9-ARCH-FLAT: ; TotalNumSgprs: 14
66+
; GFX10-ARCH-FLAT: ; TotalNumSgprs: 8
6767
define amdgpu_kernel void @no_vcc_flat() {
6868
entry:
6969
call void asm sideeffect "", "~{s7},~{flat_scratch}"()
@@ -76,11 +76,11 @@ entry:
7676
; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
7777
; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
7878

79-
; CI: ; NumSgprs: 12
80-
; VI-NOXNACK: ; NumSgprs: 14
81-
; VI-XNACK: ; NumSgprs: 14
82-
; GFX9-ARCH-FLAT: ; NumSgprs: 14
83-
; GFX10-ARCH-FLAT: ; NumSgprs: 10
79+
; CI: ; TotalNumSgprs: 12
80+
; VI-NOXNACK: ; TotalNumSgprs: 14
81+
; VI-XNACK: ; TotalNumSgprs: 14
82+
; GFX9-ARCH-FLAT: ; TotalNumSgprs: 14
83+
; GFX10-ARCH-FLAT: ; TotalNumSgprs: 10
8484
define amdgpu_kernel void @vcc_flat() {
8585
entry:
8686
call void asm sideeffect "", "~{s7},~{vcc},~{flat_scratch}"()
@@ -99,8 +99,8 @@ entry:
9999
; CI: NumSgprs: 4
100100
; VI-NOXNACK: NumSgprs: 6
101101
; VI-XNACK: NumSgprs: 6
102-
; GFX9-ARCH-FLAT: ; NumSgprs: 6
103-
; GFX10-ARCH-FLAT: ; NumSgprs: 0
102+
; GFX9-ARCH-FLAT: ; TotalNumSgprs: 6
103+
; GFX10-ARCH-FLAT: ; TotalNumSgprs: 0
104104
define amdgpu_kernel void @use_flat_scr() #0 {
105105
entry:
106106
call void asm sideeffect "; clobber ", "~{flat_scratch}"()
@@ -116,8 +116,8 @@ entry:
116116
; CI: NumSgprs: 4
117117
; VI-NOXNACK: NumSgprs: 6
118118
; VI-XNACK: NumSgprs: 6
119-
; GFX9-ARCH-FLAT: ; NumSgprs: 6
120-
; GFX10-ARCH-FLAT: ; NumSgprs: 0
119+
; GFX9-ARCH-FLAT: ; TotalNumSgprs: 6
120+
; GFX10-ARCH-FLAT: ; TotalNumSgprs: 0
121121
define amdgpu_kernel void @use_flat_scr_lo() #0 {
122122
entry:
123123
call void asm sideeffect "; clobber ", "~{flat_scratch_lo}"()
@@ -133,8 +133,8 @@ entry:
133133
; CI: NumSgprs: 4
134134
; VI-NOXNACK: NumSgprs: 6
135135
; VI-XNACK: NumSgprs: 6
136-
; GFX9-ARCH-FLAT: ; NumSgprs: 6
137-
; GFX10-ARCH-FLAT: ; NumSgprs: 0
136+
; GFX9-ARCH-FLAT: ; TotalNumSgprs: 6
137+
; GFX10-ARCH-FLAT: ; TotalNumSgprs: 0
138138
define amdgpu_kernel void @use_flat_scr_hi() #0 {
139139
entry:
140140
call void asm sideeffect "; clobber ", "~{flat_scratch_hi}"()

‎llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8,16 +8,16 @@
88
define amdgpu_kernel void @s_input_output_i128() {
99
; GFX908-LABEL: name: s_input_output_i128
1010
; GFX908: bb.0 (%ir-block.0):
11-
; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7340042 /* regdef:SGPR_128 */, def %11
11+
; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:SGPR_128 */, def %11
1212
; GFX908-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %11
13-
; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7340041 /* reguse:SGPR_128 */, [[COPY]]
13+
; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7405577 /* reguse:SGPR_128 */, [[COPY]]
1414
; GFX908-NEXT: S_ENDPGM 0
1515
;
1616
; GFX90A-LABEL: name: s_input_output_i128
1717
; GFX90A: bb.0 (%ir-block.0):
18-
; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7340042 /* regdef:SGPR_128 */, def %9
18+
; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 7405578 /* regdef:SGPR_128 */, def %9
1919
; GFX90A-NEXT: [[COPY:%[0-9]+]]:sgpr_128 = COPY %9
20-
; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7340041 /* reguse:SGPR_128 */, [[COPY]]
20+
; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 7405577 /* reguse:SGPR_128 */, [[COPY]]
2121
; GFX90A-NEXT: S_ENDPGM 0
2222
%val = tail call i128 asm sideeffect "; def $0", "=s"()
2323
call void asm sideeffect "; use $0", "s"(i128 %val)
@@ -27,16 +27,16 @@ define amdgpu_kernel void @s_input_output_i128() {
2727
define amdgpu_kernel void @v_input_output_i128() {
2828
; GFX908-LABEL: name: v_input_output_i128
2929
; GFX908: bb.0 (%ir-block.0):
30-
; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6225930 /* regdef:VReg_128 */, def %11
30+
; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6291466 /* regdef:VReg_128 */, def %11
3131
; GFX908-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY %11
32-
; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6225929 /* reguse:VReg_128 */, [[COPY]]
32+
; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6291465 /* reguse:VReg_128 */, [[COPY]]
3333
; GFX908-NEXT: S_ENDPGM 0
3434
;
3535
; GFX90A-LABEL: name: v_input_output_i128
3636
; GFX90A: bb.0 (%ir-block.0):
37-
; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6553610 /* regdef:VReg_128_Align2 */, def %9
37+
; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6619146 /* regdef:VReg_128_Align2 */, def %9
3838
; GFX90A-NEXT: [[COPY:%[0-9]+]]:vreg_128_align2 = COPY %9
39-
; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6553609 /* reguse:VReg_128_Align2 */, [[COPY]]
39+
; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6619145 /* reguse:VReg_128_Align2 */, [[COPY]]
4040
; GFX90A-NEXT: S_ENDPGM 0
4141
%val = tail call i128 asm sideeffect "; def $0", "=v"()
4242
call void asm sideeffect "; use $0", "v"(i128 %val)
@@ -46,16 +46,16 @@ define amdgpu_kernel void @v_input_output_i128() {
4646
define amdgpu_kernel void @a_input_output_i128() {
4747
; GFX908-LABEL: name: a_input_output_i128
4848
; GFX908: bb.0 (%ir-block.0):
49-
; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6160394 /* regdef:AReg_128 */, def %11
49+
; GFX908-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6225930 /* regdef:AReg_128 */, def %11
5050
; GFX908-NEXT: [[COPY:%[0-9]+]]:areg_128 = COPY %11
51-
; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6160393 /* reguse:AReg_128 */, [[COPY]]
51+
; GFX908-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6225929 /* reguse:AReg_128 */, [[COPY]]
5252
; GFX908-NEXT: S_ENDPGM 0
5353
;
5454
; GFX90A-LABEL: name: a_input_output_i128
5555
; GFX90A: bb.0 (%ir-block.0):
56-
; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6422538 /* regdef:AReg_128_Align2 */, def %9
56+
; GFX90A-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 6488074 /* regdef:AReg_128_Align2 */, def %9
5757
; GFX90A-NEXT: [[COPY:%[0-9]+]]:areg_128_align2 = COPY %9
58-
; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6422537 /* reguse:AReg_128_Align2 */, [[COPY]]
58+
; GFX90A-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 6488073 /* reguse:AReg_128_Align2 */, [[COPY]]
5959
; GFX90A-NEXT: S_ENDPGM 0
6060
%val = call i128 asm sideeffect "; def $0", "=a"()
6161
call void asm sideeffect "; use $0", "a"(i128 %val)

‎llvm/test/CodeGen/AMDGPU/ipra.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ define hidden void @func() #1 {
3030
; GCN-NOT: writelane
3131
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
3232

33-
; GCN: ; NumSgprs: 37
33+
; GCN: ; TotalNumSgprs: 37
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; GCN: ; NumVgprs: 9
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define amdgpu_kernel void @kernel_call() #0 {
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%vgpr = load volatile i32, ptr addrspace(1) undef

‎llvm/test/CodeGen/AMDGPU/min.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -591,6 +591,7 @@ define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32]
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dword s2, s[6:7], 0x28
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; VI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
594+
; VI-NEXT: s_load_dword s3, s[6:7], 0x4c
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_ashr_i32 s4, s2, 24
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; VI-NEXT: s_bfe_i32 s5, s2, 0x80010

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