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ebiggers4vtomat
ebiggers
and
4vtomat
authored
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
The RISC-V vector crypto extensions have been ratified. This patch updates the Clang and LLVM support for these extensions to be non-experimental, while leaving the C intrinsics as experimental since the C intrinsics are not yet standardized. Co-authored-by: Brandon Wu <[email protected]>
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‎clang/include/clang/Basic/riscv_vector.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2540,7 +2540,7 @@ multiclass RVVSignedWidenBinBuiltinSetVwsll
25402540

25412541
let UnMaskedPolicyScheme = HasPassthruOperand in {
25422542
// zvkb
2543-
let RequiredFeatures = ["Zvkb"] in {
2543+
let RequiredFeatures = ["Zvkb", "Experimental"] in {
25442544
defm vandn : RVVUnsignedBinBuiltinSet;
25452545
defm vbrev8 : RVVOutBuiltinSetZvbb;
25462546
defm vrev8 : RVVOutBuiltinSetZvbb;
@@ -2549,7 +2549,7 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
25492549
}
25502550

25512551
// zvbb
2552-
let RequiredFeatures = ["Zvbb"] in {
2552+
let RequiredFeatures = ["Zvbb", "Experimental"] in {
25532553
defm vbrev : RVVOutBuiltinSetZvbb;
25542554
defm vclz : RVVOutBuiltinSetZvbb;
25552555
defm vctz : RVVOutBuiltinSetZvbb;
@@ -2559,21 +2559,21 @@ let UnMaskedPolicyScheme = HasPassthruOperand in {
25592559
}
25602560

25612561
// zvbc
2562-
let RequiredFeatures = ["Zvbc"] in {
2562+
let RequiredFeatures = ["Zvbc", "Experimental"] in {
25632563
defm vclmul : RVVInt64BinBuiltinSet;
25642564
defm vclmulh : RVVInt64BinBuiltinSet;
25652565
}
25662566
}
25672567

25682568
let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
25692569
// zvkg
2570-
let RequiredFeatures = ["Zvkg"] in {
2570+
let RequiredFeatures = ["Zvkg", "Experimental"] in {
25712571
defm vghsh : RVVOutOp2BuiltinSetVVZvk;
25722572
defm vgmul : RVVOutBuiltinSetZvk<HasVV=1, HasVS=0>;
25732573
}
25742574

25752575
// zvkned
2576-
let RequiredFeatures = ["Zvkned"] in {
2576+
let RequiredFeatures = ["Zvkned", "Experimental"] in {
25772577
defm vaesdf : RVVOutBuiltinSetZvk;
25782578
defm vaesdm : RVVOutBuiltinSetZvk;
25792579
defm vaesef : RVVOutBuiltinSetZvk;
@@ -2585,28 +2585,28 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in {
25852585
}
25862586

25872587
// zvknha
2588-
let RequiredFeatures = ["Zvknha"] in {
2588+
let RequiredFeatures = ["Zvknha", "Experimental"] in {
25892589
defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"i">;
25902590
defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"i">;
25912591
defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"i">;
25922592
}
25932593

25942594
// zvknhb
2595-
let RequiredFeatures = ["Zvknhb"] in {
2595+
let RequiredFeatures = ["Zvknhb", "Experimental"] in {
25962596
defm vsha2ch : RVVOutOp2BuiltinSetVVZvk<"il">;
25972597
defm vsha2cl : RVVOutOp2BuiltinSetVVZvk<"il">;
25982598
defm vsha2ms : RVVOutOp2BuiltinSetVVZvk<"il">;
25992599
}
26002600

26012601
// zvksed
2602-
let RequiredFeatures = ["Zvksed"] in {
2602+
let RequiredFeatures = ["Zvksed", "Experimental"] in {
26032603
let UnMaskedPolicyScheme = HasPassthruOperand in
26042604
defm vsm4k : RVVOutOp1BuiltinSet<"vsm4k", "i", [["vi", "Uv", "UvUvKz"]]>;
26052605
defm vsm4r : RVVOutBuiltinSetZvk;
26062606
}
26072607

26082608
// zvksh
2609-
let RequiredFeatures = ["Zvksh"] in {
2609+
let RequiredFeatures = ["Zvksh", "Experimental"] in {
26102610
defm vsm3c : RVVOutOp2BuiltinSetVIZvk;
26112611
let UnMaskedPolicyScheme = HasPassthruOperand in
26122612
defm vsm3me : RVVOutOp1BuiltinSet<"vsm3me", "i", [["vv", "Uv", "UvUvUv"]]>;

‎clang/include/clang/Support/RISCVVIntrinsicUtils.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -485,7 +485,7 @@ class RVVIntrinsic {
485485

486486
// RVVRequire should be sync'ed with target features, but only
487487
// required features used in riscv_vector.td.
488-
enum RVVRequire : uint16_t {
488+
enum RVVRequire : uint32_t {
489489
RVV_REQ_None = 0,
490490
RVV_REQ_RV64 = 1 << 0,
491491
RVV_REQ_ZvfhminOrZvfh = 1 << 1,
@@ -503,8 +503,9 @@ enum RVVRequire : uint16_t {
503503
RVV_REQ_Zvknhb = 1 << 13,
504504
RVV_REQ_Zvksed = 1 << 14,
505505
RVV_REQ_Zvksh = 1 << 15,
506+
RVV_REQ_Experimental = 1 << 16,
506507

507-
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
508+
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental)
508509
};
509510

510511
// Raw RVV intrinsic info, used to expand later.
@@ -536,7 +537,7 @@ struct RVVIntrinsicRecord {
536537
uint8_t OverloadedSuffixSize;
537538

538539
// Required target features for this intrinsic.
539-
uint16_t RequiredExtensions;
540+
uint32_t RequiredExtensions;
540541

541542
// Supported type, mask of BasicType.
542543
uint8_t TypeRangeMask;

‎clang/lib/Basic/Targets/RISCV.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -350,6 +350,7 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
350350
.Case("riscv64", Is64Bit)
351351
.Case("32bit", !Is64Bit)
352352
.Case("64bit", Is64Bit)
353+
.Case("experimental", HasExperimental)
353354
.Default(std::nullopt);
354355
if (Result)
355356
return *Result;
@@ -382,6 +383,9 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
382383

383384
FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access");
384385

386+
if (llvm::is_contained(Features, "+experimental"))
387+
HasExperimental = true;
388+
385389
return true;
386390
}
387391

‎clang/lib/Basic/Targets/RISCV.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ class RISCVTargetInfo : public TargetInfo {
3131

3232
private:
3333
bool FastUnalignedAccess;
34+
bool HasExperimental = false;
3435

3536
public:
3637
RISCVTargetInfo(const llvm::Triple &Triple, const TargetOptions &)

‎clang/lib/Driver/ToolChains/Arch/RISCV.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,10 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
4545
(*ISAInfo)->toFeatures(
4646
Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
4747
/*AddAllExtensions=*/true);
48+
49+
if (EnableExperimentalExtensions)
50+
Features.push_back(Args.MakeArgString("+experimental"));
51+
4852
return true;
4953
}
5054

‎clang/lib/Sema/SemaChecking.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5389,7 +5389,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
53895389
QualType Op2Type = TheCall->getArg(1)->getType();
53905390
QualType Op3Type = TheCall->getArg(2)->getType();
53915391
uint64_t ElemSize = Op1Type->isRVVType(32, false) ? 32 : 64;
5392-
if (ElemSize == 64 && !TI.hasFeature("experimental-zvknhb"))
5392+
if (ElemSize == 64 && !TI.hasFeature("zvknhb"))
53935393
return Diag(TheCall->getBeginLoc(),
53945394
diag::err_riscv_type_requires_extension)
53955395
<< Op1Type << "zvknhb";

‎clang/lib/Sema/SemaRISCVVectorLookup.cpp

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -206,15 +206,16 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
206206
{"xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq},
207207
{"xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod},
208208
{"xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq},
209-
{"experimental-zvbb", RVV_REQ_Zvbb},
210-
{"experimental-zvbc", RVV_REQ_Zvbc},
211-
{"experimental-zvkb", RVV_REQ_Zvkb},
212-
{"experimental-zvkg", RVV_REQ_Zvkg},
213-
{"experimental-zvkned", RVV_REQ_Zvkned},
214-
{"experimental-zvknha", RVV_REQ_Zvknha},
215-
{"experimental-zvknhb", RVV_REQ_Zvknhb},
216-
{"experimental-zvksed", RVV_REQ_Zvksed},
217-
{"experimental-zvksh", RVV_REQ_Zvksh}};
209+
{"zvbb", RVV_REQ_Zvbb},
210+
{"zvbc", RVV_REQ_Zvbc},
211+
{"zvkb", RVV_REQ_Zvkb},
212+
{"zvkg", RVV_REQ_Zvkg},
213+
{"zvkned", RVV_REQ_Zvkned},
214+
{"zvknha", RVV_REQ_Zvknha},
215+
{"zvknhb", RVV_REQ_Zvknhb},
216+
{"zvksed", RVV_REQ_Zvksed},
217+
{"zvksh", RVV_REQ_Zvksh},
218+
{"experimental", RVV_REQ_Experimental}};
218219

219220
// Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
220221
// in RISCVVEmitter.cpp.

‎clang/lib/Support/RISCVVIntrinsicUtils.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1217,7 +1217,7 @@ raw_ostream &operator<<(raw_ostream &OS, const RVVIntrinsicRecord &Record) {
12171217
OS << (int)Record.PrototypeLength << ",";
12181218
OS << (int)Record.SuffixLength << ",";
12191219
OS << (int)Record.OverloadedSuffixSize << ",";
1220-
OS << (int)Record.RequiredExtensions << ",";
1220+
OS << Record.RequiredExtensions << ",";
12211221
OS << (int)Record.TypeRangeMask << ",";
12221222
OS << (int)Record.Log2LMULMask << ",";
12231223
OS << (int)Record.NF << ",";

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
4-
// RUN: -target-feature +experimental-zvbb \
5-
// RUN: -target-feature +experimental-zvbc \
6-
// RUN: -target-feature +experimental-zvkg \
7-
// RUN: -target-feature +experimental-zvkned \
8-
// RUN: -target-feature +experimental-zvknhb \
9-
// RUN: -target-feature +experimental-zvksed \
10-
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
4+
// RUN: -target-feature +zvbb \
5+
// RUN: -target-feature +zvbc \
6+
// RUN: -target-feature +zvkb \
7+
// RUN: -target-feature +zvkg \
8+
// RUN: -target-feature +zvkned \
9+
// RUN: -target-feature +zvknhb \
10+
// RUN: -target-feature +zvksed \
11+
// RUN: -target-feature +zvksh \
12+
// RUN: -target-feature +experimental \
13+
// RUN: -disable-O0-optnone \
1114
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
1215
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
1316

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
4-
// RUN: -target-feature +experimental-zvbb \
5-
// RUN: -target-feature +experimental-zvbc \
6-
// RUN: -target-feature +experimental-zvkg \
7-
// RUN: -target-feature +experimental-zvkned \
8-
// RUN: -target-feature +experimental-zvknhb \
9-
// RUN: -target-feature +experimental-zvksed \
10-
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
4+
// RUN: -target-feature +zvbb \
5+
// RUN: -target-feature +zvbc \
6+
// RUN: -target-feature +zvkb \
7+
// RUN: -target-feature +zvkg \
8+
// RUN: -target-feature +zvkned \
9+
// RUN: -target-feature +zvknhb \
10+
// RUN: -target-feature +zvksed \
11+
// RUN: -target-feature +zvksh \
12+
// RUN: -target-feature +experimental \
13+
// RUN: -disable-O0-optnone \
1114
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
1215
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
1316

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
4-
// RUN: -target-feature +experimental-zvbb \
5-
// RUN: -target-feature +experimental-zvbc \
6-
// RUN: -target-feature +experimental-zvkg \
7-
// RUN: -target-feature +experimental-zvkned \
8-
// RUN: -target-feature +experimental-zvknhb \
9-
// RUN: -target-feature +experimental-zvksed \
10-
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
4+
// RUN: -target-feature +zvbb \
5+
// RUN: -target-feature +zvbc \
6+
// RUN: -target-feature +zvkb \
7+
// RUN: -target-feature +zvkg \
8+
// RUN: -target-feature +zvkned \
9+
// RUN: -target-feature +zvknhb \
10+
// RUN: -target-feature +zvksed \
11+
// RUN: -target-feature +zvksh \
12+
// RUN: -target-feature +experimental \
13+
// RUN: -disable-O0-optnone \
1114
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
1215
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
1316

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
4-
// RUN: -target-feature +experimental-zvbb \
5-
// RUN: -target-feature +experimental-zvbc \
6-
// RUN: -target-feature +experimental-zvkg \
7-
// RUN: -target-feature +experimental-zvkned \
8-
// RUN: -target-feature +experimental-zvknhb \
9-
// RUN: -target-feature +experimental-zvksed \
10-
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
4+
// RUN: -target-feature +zvbb \
5+
// RUN: -target-feature +zvbc \
6+
// RUN: -target-feature +zvkb \
7+
// RUN: -target-feature +zvkg \
8+
// RUN: -target-feature +zvkned \
9+
// RUN: -target-feature +zvknhb \
10+
// RUN: -target-feature +zvksed \
11+
// RUN: -target-feature +zvksh \
12+
// RUN: -target-feature +experimental \
13+
// RUN: -disable-O0-optnone \
1114
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
1215
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
1316

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
4-
// RUN: -target-feature +experimental-zvbb \
5-
// RUN: -target-feature +experimental-zvbc \
6-
// RUN: -target-feature +experimental-zvkg \
7-
// RUN: -target-feature +experimental-zvkned \
8-
// RUN: -target-feature +experimental-zvknhb \
9-
// RUN: -target-feature +experimental-zvksed \
10-
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
4+
// RUN: -target-feature +zvbb \
5+
// RUN: -target-feature +zvbc \
6+
// RUN: -target-feature +zvkb \
7+
// RUN: -target-feature +zvkg \
8+
// RUN: -target-feature +zvkned \
9+
// RUN: -target-feature +zvknhb \
10+
// RUN: -target-feature +zvksed \
11+
// RUN: -target-feature +zvksh \
12+
// RUN: -target-feature +experimental \
13+
// RUN: -disable-O0-optnone \
1114
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
1215
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
1316

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
4-
// RUN: -target-feature +experimental-zvbb \
5-
// RUN: -target-feature +experimental-zvbc \
6-
// RUN: -target-feature +experimental-zvkg \
7-
// RUN: -target-feature +experimental-zvkned \
8-
// RUN: -target-feature +experimental-zvknhb \
9-
// RUN: -target-feature +experimental-zvksed \
10-
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
4+
// RUN: -target-feature +zvbb \
5+
// RUN: -target-feature +zvbc \
6+
// RUN: -target-feature +zvkb \
7+
// RUN: -target-feature +zvkg \
8+
// RUN: -target-feature +zvkned \
9+
// RUN: -target-feature +zvknhb \
10+
// RUN: -target-feature +zvksed \
11+
// RUN: -target-feature +zvksh \
12+
// RUN: -target-feature +experimental \
13+
// RUN: -disable-O0-optnone \
1114
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
1215
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
1316

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
4-
// RUN: -target-feature +experimental-zvbb \
5-
// RUN: -target-feature +experimental-zvbc \
6-
// RUN: -target-feature +experimental-zvkg \
7-
// RUN: -target-feature +experimental-zvkned \
8-
// RUN: -target-feature +experimental-zvknhb \
9-
// RUN: -target-feature +experimental-zvksed \
10-
// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
4+
// RUN: -target-feature +zvbb \
5+
// RUN: -target-feature +zvbc \
6+
// RUN: -target-feature +zvkb \
7+
// RUN: -target-feature +zvkg \
8+
// RUN: -target-feature +zvkned \
9+
// RUN: -target-feature +zvknhb \
10+
// RUN: -target-feature +zvksed \
11+
// RUN: -target-feature +zvksh \
12+
// RUN: -target-feature +experimental \
13+
// RUN: -disable-O0-optnone \
1114
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
1215
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
1316

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,16 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
4-
// RUN: -target-feature +experimental-zvbb \
5-
// RUN: -target-feature +experimental-zvbc \
6-
// RUN: -target-feature +experimental-zvkb \
7-
// RUN: -target-feature +experimental-zvkg \
8-
// RUN: -target-feature +experimental-zvkned \
9-
// RUN: -target-feature +experimental-zvknhb \
10-
// RUN: -target-feature +experimental-zvksed \
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// RUN: -target-feature +experimental-zvksh -disable-O0-optnone \
4+
// RUN: -target-feature +zvbb \
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// RUN: -target-feature +zvbc \
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// RUN: -target-feature +zvkb \
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// RUN: -target-feature +zvkg \
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// RUN: -target-feature +zvkned \
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// RUN: -target-feature +zvknhb \
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// RUN: -target-feature +zvksed \
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// RUN: -target-feature +zvksh \
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// RUN: -target-feature +experimental \
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// RUN: -disable-O0-optnone \
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// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
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// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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