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[HLSL][DXIL] Implement WaveGetLaneIndex
- add additional lowering for directx backend in CGBuiltin.cpp - add directx intrinsic to IntrinscsDirectX.td - add semantic check of arguments in SemaHLSL.cpp - add mapping to DXIL op in DXIL.td - add testing of semantics in WaveGetLaneIndex-errors.hlsl - add testing of dxil lowering in WaveGetLaneIndex.ll
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6 files changed

+43
-3
lines changed

6 files changed

+43
-3
lines changed

clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18827,9 +18827,18 @@ case Builtin::BI__builtin_hlsl_elementwise_isinf: {
1882718827
ArrayRef<Value *>{Op0, Op1}, nullptr, "hlsl.step");
1882818828
}
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case Builtin::BI__builtin_hlsl_wave_get_lane_index: {
18830-
return EmitRuntimeCall(CGM.CreateRuntimeFunction(
18831-
llvm::FunctionType::get(IntTy, {}, false), "__hlsl_wave_get_lane_index",
18832-
{}, false, true));
18830+
switch (CGM.getTarget().getTriple().getArch()) {
18831+
case llvm::Triple::dxil:
18832+
return EmitRuntimeCall(Intrinsic::getDeclaration(
18833+
&CGM.getModule(), Intrinsic::dx_waveGetLaneIndex));
18834+
case llvm::Triple::spirv:
18835+
return EmitRuntimeCall(CGM.CreateRuntimeFunction(
18836+
llvm::FunctionType::get(IntTy, {}, false),
18837+
"__hlsl_wave_get_lane_index", {}, false, true));
18838+
default:
18839+
llvm_unreachable(
18840+
"Intrinsic waveGetLaneIndex not supported by target architecture");
18841+
}
1883318842
}
1883418843
case Builtin::BI__builtin_hlsl_wave_is_first_lane: {
1883518844
Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveIsFirstLaneIntrinsic();

clang/lib/Sema/SemaHLSL.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1956,6 +1956,11 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
19561956
return true;
19571957
break;
19581958
}
1959+
case Builtin::BI__builtin_hlsl_wave_get_lane_index: {
1960+
if (SemaRef.checkArgCount(TheCall, 0))
1961+
return true;
1962+
break;
1963+
}
19591964
case Builtin::BI__builtin_elementwise_acos:
19601965
case Builtin::BI__builtin_elementwise_asin:
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case Builtin::BI__builtin_elementwise_atan:
Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected
2+
3+
int test_too_many_arg(int x) {
4+
return __builtin_hlsl_wave_get_lane_index(x);
5+
// expected-error@-1 {{too many arguments to function call, expected 0, have 1}}
6+
}

llvm/include/llvm/IR/IntrinsicsDirectX.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,7 @@ def int_dx_imad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLV
8282
def int_dx_umad : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
8383
def int_dx_normalize : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>;
8484
def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
85+
def int_dx_waveGetLaneIndex : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent, IntrNoMem]>;
8586
def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>;
8687
def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>;
8788
def int_dx_step : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty, LLVMMatchType<0>], [IntrNoMem]>;

llvm/lib/Target/DirectX/DXIL.td

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -801,3 +801,12 @@ def WaveIsFirstLane : DXILOp<110, waveIsFirstLane> {
801801
let stages = [Stages<DXIL1_0, [all_stages]>];
802802
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
803803
}
804+
805+
def WaveGetLaneIndex : DXILOp<111, waveGetLaneIndex> {
806+
let Doc = "returns the index of the current lane in the wave";
807+
let LLVMIntrinsic = int_dx_waveGetLaneIndex;
808+
let arguments = [];
809+
let result = Int32Ty;
810+
let stages = [Stages<DXIL1_0, [all_stages]>];
811+
let attributes = [Attributes<DXIL1_0, [ReadNone]>];
812+
}
Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s
2+
3+
define void @main() {
4+
entry:
5+
; CHECK: call i32 @dx.op.waveGetLaneIndex(i32 111)
6+
%0 = call i32 @llvm.dx.waveGetLaneIndex()
7+
ret void
8+
}
9+
10+
declare i32 @llvm.dx.waveGetLaneIndex()

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