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[instcombine] Improve coverage for reductions of i1 types
In advance of an upcoming change to generalize some of this to scalable vector types.
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‎llvm/test/Transforms/InstCombine/vector-logical-reductions.ll

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@@ -11,6 +11,15 @@ define i1 @reduction_logical_or(<4 x i1> %x) {
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ret i1 %r
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}
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define i1 @reduction_logical_or_nxv2i1(<vscale x 2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_or_nxv2i1(
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; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_and(<4 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_and(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
@@ -21,6 +30,131 @@ define i1 @reduction_logical_and(<4 x i1> %x) {
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ret i1 %r
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}
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define i1 @reduction_logical_and_nxv2i1(<vscale x 2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_and_nxv2i1(
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; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_mul(<2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_mul(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
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; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[TMP1]], -1
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.mul.v4i1(<2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_mul_nxv2i1(<vscale x 2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_mul_nxv2i1(
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; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.mul.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.mul.nxv2i1(<vscale x 2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_xor(<2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_xor(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
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; CHECK-NEXT: [[TMP2:%.*]] = call range(i2 0, -1) i2 @llvm.ctpop.i2(i2 [[TMP1]])
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; CHECK-NEXT: [[R:%.*]] = trunc i2 [[TMP2]] to i1
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.xor.v4i1(<2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_xor_nxv2i1(<vscale x 2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_xor_nxv2i1(
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; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_smin(<2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_smin(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
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; CHECK-NEXT: [[R:%.*]] = icmp ne i2 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.smin.v4i1(<2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_smin_nxv2i1(<vscale x 2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_smin_nxv2i1(
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; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_smax(<2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_smax(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
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; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[TMP1]], -1
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.smax.v4i1(<2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_smax_nxv2i1(<vscale x 2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_smax_nxv2i1(
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; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_umin(<2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_umin(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
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; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[TMP1]], -1
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.umin.v4i1(<2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_umin_nxv2i1(<vscale x 2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_umin_nxv2i1(
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; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_umax(<2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_umax(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
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; CHECK-NEXT: [[R:%.*]] = icmp ne i2 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.umax.v4i1(<2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_umax_nxv2i1(<vscale x 2 x i1> %x) {
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; CHECK-LABEL: @reduction_logical_umax_nxv2i1(
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; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
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; CHECK-NEXT: ret i1 [[R]]
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;
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%r = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> %x)
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ret i1 %r
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}
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define i1 @reduction_logical_or_reverse_nxv2i1(<vscale x 2 x i1> %p) {
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; CHECK-LABEL: @reduction_logical_or_reverse_nxv2i1(
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; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[P:%.*]])
@@ -93,5 +227,15 @@ declare i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1>)
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declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
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declare i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1>)
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declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
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declare i1 @llvm.vector.reduce.mul.nxv2i1(<vscale x 2 x i1>)
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declare i1 @llvm.vector.reduce.mul.v2i1(<2 x i1>)
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declare i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1>)
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declare i1 @llvm.vector.reduce.smin.v2i1(<2 x i1>)
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declare i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1>)
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declare i1 @llvm.vector.reduce.smax.v2i1(<2 x i1>)
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declare i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1>)
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declare i1 @llvm.vector.reduce.umin.v2i1(<2 x i1>)
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declare i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1>)
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declare i1 @llvm.vector.reduce.umax.v2i1(<2 x i1>)
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declare <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1>)
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declare <2 x i1> @llvm.vector.reverse.v2i1(<2 x i1>)

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