@@ -29,7 +29,6 @@ struct CPUInfo {
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StringLiteral Name;
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CPUKind Kind;
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StringLiteral DefaultMarch;
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- bool isInvalid () const { return DefaultMarch.empty (); }
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bool is64Bit () const { return DefaultMarch.starts_with (" rv64" ); }
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};
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@@ -55,12 +54,13 @@ bool parseCPU(StringRef CPU, bool IsRV64) {
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}
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bool parseTuneCPU (StringRef TuneCPU, bool IsRV64) {
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- CPUKind Kind = llvm::StringSwitch<CPUKind>(TuneCPU)
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- #define TUNE_PROC (ENUM, NAME ) .Case(NAME, CK_##ENUM)
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+ std::optional<CPUKind> Kind =
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+ llvm::StringSwitch<std::optional<CPUKind>>(TuneCPU)
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+ #define TUNE_PROC (ENUM, NAME ) .Case(NAME, CK_##ENUM)
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#include " llvm/TargetParser/RISCVTargetParserDef.inc"
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- .Default (CK_INVALID );
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+ .Default (std::nullopt );
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- if (Kind != CK_INVALID )
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+ if (Kind. has_value () )
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return true ;
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// Fallback to parsing as a CPU.
@@ -76,14 +76,14 @@ StringRef getMArchFromMcpu(StringRef CPU) {
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void fillValidCPUArchList (SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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- if (C. Kind != CK_INVALID && IsRV64 == C.is64Bit ())
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+ if (IsRV64 == C.is64Bit ())
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Values.emplace_back (C.Name );
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}
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}
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void fillValidTuneCPUArchList (SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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- if (C. Kind != CK_INVALID && IsRV64 == C.is64Bit ())
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+ if (IsRV64 == C.is64Bit ())
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Values.emplace_back (C.Name );
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}
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#define TUNE_PROC (ENUM, NAME ) Values.emplace_back(StringRef(NAME));
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