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[RISCV] Remove INVALID from the list of CPUs in RISCVTargetParser. NFC
This value is never used outside and is only used as a sentinel internally which we can solve with other means.
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2 files changed

+7
-8
lines changed

2 files changed

+7
-8
lines changed

llvm/lib/TargetParser/RISCVTargetParser.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,6 @@ struct CPUInfo {
2929
StringLiteral Name;
3030
CPUKind Kind;
3131
StringLiteral DefaultMarch;
32-
bool isInvalid() const { return DefaultMarch.empty(); }
3332
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
3433
};
3534

@@ -55,12 +54,13 @@ bool parseCPU(StringRef CPU, bool IsRV64) {
5554
}
5655

5756
bool parseTuneCPU(StringRef TuneCPU, bool IsRV64) {
58-
CPUKind Kind = llvm::StringSwitch<CPUKind>(TuneCPU)
59-
#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
57+
std::optional<CPUKind> Kind =
58+
llvm::StringSwitch<std::optional<CPUKind>>(TuneCPU)
59+
#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
6060
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
61-
.Default(CK_INVALID);
61+
.Default(std::nullopt);
6262

63-
if (Kind != CK_INVALID)
63+
if (Kind.has_value())
6464
return true;
6565

6666
// Fallback to parsing as a CPU.
@@ -76,14 +76,14 @@ StringRef getMArchFromMcpu(StringRef CPU) {
7676

7777
void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
7878
for (const auto &C : RISCVCPUInfo) {
79-
if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
79+
if (IsRV64 == C.is64Bit())
8080
Values.emplace_back(C.Name);
8181
}
8282
}
8383

8484
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
8585
for (const auto &C : RISCVCPUInfo) {
86-
if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
86+
if (IsRV64 == C.is64Bit())
8787
Values.emplace_back(C.Name);
8888
}
8989
#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));

llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,6 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
5252
<< "#define PROC(ENUM, NAME, DEFAULT_MARCH)\n"
5353
<< "#endif\n\n";
5454

55-
OS << "PROC(INVALID, {\"invalid\"}, {\"\"})\n";
5655
// Iterate on all definition records.
5756
for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
5857
std::string MArch = Rec->getValueAsString("DefaultMarch").str();

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