[WebAssembly] Add 3 more optimization for any/all

all_true (setcc x, 0, eq) -> not any_true
any_true (setcc x, 0, ne) -> any_true
all_true (setcc x, 0, ne) -> all_true

Author: badumbatish

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

@@ -3240,40 +3240,53 @@ static SDValue performBitcastCombine(SDNode *N,
   return SDValue();
 }
 
-static SDValue performAnyTrueCombine(SDNode *N, SelectionDAG &DAG) {
-  // any_true (setcc <X>, 0, eq)
-  // => not (all_true X)
-
-  SDLoc DL(N);
+static SDValue performAnyAllCombine(SDNode *N, SelectionDAG &DAG) {
+  // any_true (setcc <X>, 0, eq) => (not (all_true X))
+  // all_true (setcc <X>, 0, eq) => (not (any_true X))
+  // any_true (setcc <X>, 0, ne) => (any_true X)
+  // all_true (setcc <X>, 0, ne) => (all_true X)
   assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN);
-  if (N->getConstantOperandVal(0) != Intrinsic::wasm_anytrue)
-    return SDValue();
+  using namespace llvm::SDPatternMatch;
+  SDLoc DL(N);
+  static auto SimdCombiner =
+      [&](Intrinsic::WASMIntrinsics InPre, ISD::CondCode SetType,
+          Intrinsic::WASMIntrinsics InPost, bool ShouldInvert) -> SDValue {
+    if (N->getConstantOperandVal(0) != InPre)
+      return SDValue();
 
-  SDValue SetCC = N->getOperand(1);
-  if (SetCC.getOpcode() != ISD::SETCC)
-    return SDValue();
+    SDValue LHS;
+    if (!sd_match(N->getOperand(1), m_c_SetCC(m_Value(LHS), m_Zero(),
+                                              m_SpecificCondCode(SetType))))
+      return SDValue();
 
-  SDValue LHS = SetCC->getOperand(0);
-  SDValue RHS = SetCC->getOperand(1);
-  ISD::CondCode Cond = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
-  EVT LT = LHS.getValueType();
-  unsigned NumElts = LT.getVectorNumElements();
-  if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
-    return SDValue();
+    EVT LT = LHS.getValueType();
+    unsigned NumElts = LT.getVectorNumElements();
+    if (LT.getScalarSizeInBits() > 128 / NumElts)
+      return SDValue();
 
-  EVT Width = MVT::getIntegerVT(128 / NumElts);
+    SDValue Ret = DAG.getZExtOrTrunc(
+        DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
+                    {DAG.getConstant(InPost, DL, MVT::i32), LHS}),
+        DL, MVT::i1);
+    if (ShouldInvert)
+      Ret = DAG.getNOT(DL, Ret, MVT::i1);
+    return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
+  };
 
-  if (!isNullOrNullSplat(RHS) || Cond != ISD::SETEQ)
-    return SDValue();
+  if (SDValue AnyTrueEQ = SimdCombiner(Intrinsic::wasm_anytrue, ISD::SETEQ,
+                                       Intrinsic::wasm_alltrue, true))
+    return AnyTrueEQ;
+  if (SDValue AllTrueEQ = SimdCombiner(Intrinsic::wasm_alltrue, ISD::SETEQ,
+                                       Intrinsic::wasm_anytrue, true))
+    return AllTrueEQ;
+  if (SDValue AnyTrueNE = SimdCombiner(Intrinsic::wasm_anytrue, ISD::SETNE,
+                                       Intrinsic::wasm_anytrue, false))
+    return AnyTrueNE;
+  if (SDValue AllTrueNE = SimdCombiner(Intrinsic::wasm_alltrue, ISD::SETNE,
+                                       Intrinsic::wasm_alltrue, false))
+    return AllTrueNE;
 
-  SDValue Ret = DAG.getZExtOrTrunc(
-      DAG.getNode(
-          ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
-          {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32),
-           DAG.getSExtOrTrunc(LHS, DL, LT.changeVectorElementType(Width))}),
-      DL, MVT::i1);
-  Ret = DAG.getNOT(DL, Ret, MVT::i1);
-  return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
+  return SDValue();
 }
 
 template <int MatchRHS, ISD::CondCode MatchCond, bool RequiresNegate,
@@ -3465,8 +3478,8 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::TRUNCATE:
     return performTruncateCombine(N, DCI);
   case ISD::INTRINSIC_WO_CHAIN: {
-    if (auto AnyTrueCombine = performAnyTrueCombine(N, DCI.DAG))
-      return AnyTrueCombine;
+    if (auto AnyAllCombine = performAnyAllCombine(N, DCI.DAG))
+      return AnyAllCombine;
     return performLowerPartialReduction(N, DCI.DAG);
   }
   case ISD::MUL:

llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll

@@ -89,10 +89,8 @@ define i32 @any_true_1_4_i32(<4 x i32> %v) {
 ; CHECK-LABEL: any_true_1_4_i32:
 ; CHECK:         .functype any_true_1_4_i32 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0
-; CHECK-NEXT:    i32x4.ne $push1=, $0, $pop0
-; CHECK-NEXT:    v128.any_true $push2=, $pop1
-; CHECK-NEXT:    return $pop2
+; CHECK-NEXT:    v128.any_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp ne <4 x i32> %v, zeroinitializer
   %2 = bitcast <4 x i1> %1 to i4
   %3 = icmp ne i4 %2, 0
@@ -109,14 +107,8 @@ define i32 @any_true_2_4_i32(<4 x i32> %v) {
 ; CHECK-LABEL: any_true_2_4_i32:
 ; CHECK:         .functype any_true_2_4_i32 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0
-; CHECK-NEXT:    i32x4.eq $push1=, $0, $pop0
-; CHECK-NEXT:    i32x4.all_true $push2=, $pop1
-; CHECK-NEXT:    i32.const $push3=, -1
-; CHECK-NEXT:    i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT:    i32.const $push5=, 1
-; CHECK-NEXT:    i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT:    return $pop6
+; CHECK-NEXT:    v128.any_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp eq <4 x i32> %v, zeroinitializer
   %2 = bitcast <4 x i1> %1 to i4
   %3 = icmp ne i4 %2, -1
@@ -132,10 +124,8 @@ define i32 @all_true_2_4_i32(<4 x i32> %v) {
 ; CHECK-LABEL: all_true_2_4_i32:
 ; CHECK:         .functype all_true_2_4_i32 (v128) -> (i32)
 ; CHECK-NEXT:  # %bb.0:
-; CHECK-NEXT:    v128.const $push0=, 0, 0, 0, 0
-; CHECK-NEXT:    i32x4.ne $push1=, $0, $pop0
-; CHECK-NEXT:    i32x4.all_true $push2=, $pop1
-; CHECK-NEXT:    return $pop2
+; CHECK-NEXT:    i32x4.all_true $push0=, $0
+; CHECK-NEXT:    return $pop0
   %1 = icmp ne <4 x i32> %v, zeroinitializer
   %2 = bitcast <4 x i1> %1 to i4
   %3 = icmp eq i4 %2, -1